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Balasubramaniyan, A., S. Saravanan and H.N. Upadhyay, 2013. Run-length based efficient compression for system-on-chip. J. Artif. Intel., 6: 107-111. CrossRefDirect Link |
Saravanan, S. and H.N. Upadhyay, 2012. Achieving low power test pattern by efficient compaction method for soc design. J. Artif. Intel., 5: 244-248. CrossRefDirect Link |
How to cite this article
Mehdi Azimipour and Mohammad Eshghi, 2008. Parallel Circular-Scan Architecture. Journal of Applied Sciences, 8: 2083-2090.
DOI: 10.3923/jas.2008.2083.2090
URL: https://scialert.net/abstract/?doi=jas.2008.2083.2090
DOI: 10.3923/jas.2008.2083.2090
URL: https://scialert.net/abstract/?doi=jas.2008.2083.2090