
	Journal of Artificial Intelligence
	Year: 2013 \| Volume: 6 \| Issue: 1 \| Page No.: 107-111 DOI: 10.3923/jai.2013.107.111

Run-Length Based Efficient Compression for System-on-Chip

A. Balasubramaniyan, S. Saravanan and Har Narayan Upadhyay

Abstract: Large test data volume is one of the major problems in the emerging System-on-Chip (SoC) and this can be reduced by test data compression techniques. Variable-to-variable length compression is one among the test data compression techniques. This study demonstrates a variable-to-variable length based compression technique called Run-Length based Efficient Compression. The patterns which are selected for doing compression can be partitioned into blocks having equal width. The partitioned blocks can be compared with the adjacent one and can be merged. A control code is used to denote the number of blocks merged. The proposed method can be tested by calculating the effect of compression on larger ISCAS’89 benchmark circuits.

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How to cite this article:

A. Balasubramaniyan, S. Saravanan and Har Narayan Upadhyay, 2013. Run-Length Based Efficient Compression for System-on-Chip. Journal of Artificial Intelligence, 6: 107-111.

DOI: 10.3923/jai.2013.107.111

URL: https://scialert.net/abstract/?doi=jai.2013.107.111

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