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Journal of Artificial Intelligence
  Year: 2012 | Volume: 5 | Issue: 4 | Page No.: 244-248
DOI: 10.3923/jai.2012.244.248
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Achieving Low Power Test Pattern By Efficient Compaction Method For SoC Design

S. Saravanan and Har Narayan Upadhyay

Present System-on-Chip (SoC) contains various design models and all the design components are integrated into single Integrated Chip (IC). Thus total volume of SoC test pattern is also growing in complex manner. This huge test pattern also invokes various challenges in switching power, memory space and accessing time. The problem on huge test pattern involved for scan based testing is focused in this research. Coloring algorithm is proposed to compact test pattern. Utilization of unspecified test pattern promises more compaction in coloring algorithm. This proposed method never contains any extra silicon area overhead. Due to this advantage, proposed technique is more suitable for reduction of test pattern. An experimental result produces significant reduction in above said problems and tested with ISCAS89 benchmark circuits.
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  •    Parallel Circular-Scan Architecture
  •    High Degree of Testability Using Full Scan Chain and ATPG-An Industrial Perspective
How to cite this article:

S. Saravanan and Har Narayan Upadhyay, 2012. Achieving Low Power Test Pattern By Efficient Compaction Method For SoC Design. Journal of Artificial Intelligence, 5: 244-248.

DOI: 10.3923/jai.2012.244.248






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