Citation to this article as recorded by
Elamaran, V., G. Rajkumar, S.S. Rajpurohit and R.A. Krishnan, 2014. A novel low power adder-subtractor using efficient XOR gates. J. Applied Sci., 14: 1623-1627. CrossRefDirect Link |
Rajesh, K.S.S.K., S.H.H. Subramani and V. Elamaran, 2014. CMOS VLSI design of low power comparator logic circuits. Asian J. Sci. Res., 7: 238-247. CrossRefDirect Link |
Reddy, N.S.S., 2011. Minimization of power dissipation in 16 bit processor using low power tecniques. Asian J. Applied Sci., 4: 657-662. CrossRefDirect Link |
Subramani, S.H.H., K.S.S.K. Rajesh and V. Elamaran, 2014. Low energy, low power adder logic cells: A CMOS VLSI implementation. Asian J. Sci. Res., 7: 248-255. CrossRefDirect Link |
V. Elamaran, N. Raju , Anooj Krishnan , Kalagarla Abhiram 2014. CMOS VLSI Implementation of Adders with Low Leakage Power J. Applied Sci., 14: 1550-1556. CrossRef |
Citation to this article as recorded by
Minimization of Power Dissipation in 16 Bit Processor using Low Power Tecniques Asian Journal of Applied Sciences Vol. 4, Issue 6, 657, 2011 |
How to cite this article
T. Vigneswaran and P. Subbarami Reddy, 2006. A Novel Low Power 8 Bit Adder Unit with Adaptive Supply Voltage. Journal of Applied Sciences, 6: 2936-2939.
DOI: 10.3923/jas.2006.2936.2939
URL: https://scialert.net/abstract/?doi=jas.2006.2936.2939
DOI: 10.3923/jas.2006.2936.2939
URL: https://scialert.net/abstract/?doi=jas.2006.2936.2939