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Journal of Applied Sciences
  Year: 2006 | Volume: 6 | Issue: 14 | Page No.: 2936-2939
DOI: 10.3923/jas.2006.2936.2939
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A Novel Low Power 8 Bit Adder Unit with Adaptive Supply Voltage

T. Vigneswaran and P. Subbarami Reddy

Demands for the low power VLSI have been pushing the development of aggressive design methodologies to reduce the power consumption drastically. To meet the growing demand, we propose a low power 8 bit adder unit, which adaptively selects supply voltages based on the input vector patterns. We prototyped an 8-bit ripple carry adder unit and analyzed the power consumption and performance in details. Results show 80.2% improvement in power consumption without affecting the overall performance of the given design.
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  •    Low Energy, Low Power Adder Logic Cells: A CMOS VLSI Implementation
  •    CMOS VLSI Design of Low Power Comparator Logic Circuits
  •    A Novel Low Power Adder-Subtractor using Efficient XOR Gates
  •    CMOS VLSI Implementation of Adders with Low Leakage Power
How to cite this article:

T. Vigneswaran and P. Subbarami Reddy , 2006. A Novel Low Power 8 Bit Adder Unit with Adaptive Supply Voltage. Journal of Applied Sciences, 6: 2936-2939.

DOI: 10.3923/jas.2006.2936.2939






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