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Journal of Applied Sciences
  Year: 2014 | Volume: 14 | Issue: 14 | Page No.: 1550-1556
DOI: 10.3923/jas.2014.1550.1556
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CMOS VLSI Implementation of Adders with Low Leakage Power

V. Elamaran, N. Raju , Anooj Krishnan and Kalagarla Abhiram

Due to the semiconductor technology revolution, portable consumer electronic products are made with more features. The power dissipation factor is important since those systems are built with plenty of transistors. As the sizes of the transistors shrink and the technology scales, leakage current increases considerably thereby dominates dynamic power. Since most of the leakage currents like gate channel leakage, diode junction reverse-biased current and sub-threshold channel leakage are process dependent, sub-threshold leakage alone is concentrated here as a major concern. This study provides performance comparison analysis of a single-bit adder using sleep, stack, sleepy stack and sleepy keeper approaches. To achieve power reduction during the sleep or standby mode, the operating supply voltage can be disconnected to the rest of the circuit with an additional sleepy transistor. A leakage power reduction can also be achived by stack method in which the transistor length can be increased or by increasing the width of the corresponding transistors. A dynamic power reduction will also be achieved by implementing methods like clock gating, multiple threshold CMOS (Complementary Metal-Oxide-Semiconductor) and dynamic threshold CMOS, etc. A small amount of power reduction in a full adder will result a dramatic change of overall power of the system. A sleepy method provide a better leakage power reduction with 12.486 μW as compared to other techniques. All the results can be verified using Electronic Design Automation (EDA) tools like DSCH (Digital Schematic) and Microwind layout editor software tool. Results show that sleepy stack approach provide better leakage reduction at the cost of area.
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  •    New Low-leakage Flip-flops with Power-gating Scheme for Ultra-low Power Systems
  •    Leakage Tolerant, Noise Immune Domino Logic for Circuit Design in the Ultra Deep Submicron CMOS Technology for High Fan-in Gates
  •    A New Leakage Power Reduction Technique for CMOS VLSI Circuits
  •    Minimization of Power Dissipation in 16 Bit Processor using Low Power Tecniques
How to cite this article:

V. Elamaran, N. Raju , Anooj Krishnan and Kalagarla Abhiram , 2014. CMOS VLSI Implementation of Adders with Low Leakage Power. Journal of Applied Sciences, 14: 1550-1556.

DOI: 10.3923/jas.2014.1550.1556






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