V. Elamaran
Department of ECE, School of EEE, SASTRA University, 613 401, India
N. Raju
Department of ECE, School of EEE, SASTRA University, 613 401, India
Anooj Krishnan
Department of ECE, School of EEE, SASTRA University, 613 401, India
Kalagarla Abhiram
Department of ECE, School of EEE, SASTRA University, 613 401, India
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How to cite this article
V. Elamaran, N. Raju, Anooj Krishnan and Kalagarla Abhiram, 2014. CMOS VLSI Implementation of Adders with Low Leakage Power. Journal of Applied Sciences, 14: 1550-1556.
DOI: 10.3923/jas.2014.1550.1556
URL: https://scialert.net/abstract/?doi=jas.2014.1550.1556
DOI: 10.3923/jas.2014.1550.1556
URL: https://scialert.net/abstract/?doi=jas.2014.1550.1556