Citation to this article as recorded by
Elamaran, V. and H.N. Upadhyay, 2015. Low power digital barrel shifter datapath circuits using microwind layout editor with high reliability. Asian J. Sci. Res., 8: 478-489. CrossRefDirect Link |
V. Elamaran and H.N. Upadhyay, 2015. CMOS VLSI design of low power SRAM cell architectures with new TMR: a layout approach. Asian J. Sci. Res., 8: 466-477. CrossRefDirect Link |
How to cite this article
K.S.S.K. Rajesh, S. Hari Hara Subramani and V. Elamaran, 2014. CMOS VLSI Design of Low Power Comparator Logic Circuits. Asian Journal of Scientific Research, 7: 238-247.
DOI: 10.3923/ajsr.2014.238.247
URL: https://scialert.net/abstract/?doi=ajsr.2014.238.247
DOI: 10.3923/ajsr.2014.238.247
URL: https://scialert.net/abstract/?doi=ajsr.2014.238.247