Subscribe Now Subscribe Today
Science Alert
 
Blue
   
Curve Top
Asian Journal of Scientific Research
  Year: 2014 | Volume: 7 | Issue: 2 | Page No.: 238-247
DOI: 10.3923/ajsr.2014.238.247
 
Facebook Twitter Digg Reddit Linkedin StumbleUpon E-mail

CMOS VLSI Design of Low Power Comparator Logic Circuits

K.S.S.K. Rajesh, S. Hari Hara Subramani and V. Elamaran

Abstract:
As the demand of portable consumer electronic products increases rapidly and the chip size decreases, designers are facing many challenges towards the circuit area and power. Decades ago, engineers worried about the speed of operation of the system. They are able to manage this challenge by reducing the length of the transistors. But still, low power sub-system circuit designs are the toughest job by the engineers. Since the battery technology does not grow rapidly, still people are forced to use such a large size batteries in the system to operate. Engineers are not concentrating much about the size reduction of batteries because of huge risk factors like highly explosive. The only choice with the designers to produce a system which will consume low power is the best design with the circuit. Complementary Metal Oxide Semiconductor (CMOS) logic styles are much popular for dissipating less energy or low power. Here we present 8-bit comparator logic circuits with different logic styles like conventional CMOS, Dynamic CMOS and Domino CMOS. Initially, single-bit comparator is designed and the functionality is verified with all kind of styles. Using this design, by connecting them in a cascaded manner 4-bit comparator and 8-bit comparator are designed. Comparator logic circuits are very important data path module in a processor based systems for the comparison of two words. We simulate all the designs using DSCH (Digital Schematic) and Microwind Electronic Design Automation (EDA) tools with the functional verification of Greater Than (GT), Less Than (LT) and Equal (EQ) among the two words. Timing diagram and power dissipation of the designs are tabulated with propagation delay.
PDF Fulltext XML References Citation Report Citation
 RELATED ARTICLES:
  •    Low Power Digital Barrel Shifter Datapath Circuits Using Microwind Layout Editor with High Reliability
  •    CMOS VLSI Design of Low Power SRAM Cell Architectures with New TMR: A Layout Approach
  •    New Low-leakage Flip-flops with Power-gating Scheme for Ultra-low Power Systems
  •    Leakage Tolerant, Noise Immune Domino Logic for Circuit Design in the Ultra Deep Submicron CMOS Technology for High Fan-in Gates
  •    A New Leakage Power Reduction Technique for CMOS VLSI Circuits
  •    Minimization of Power Dissipation in 16 Bit Processor using Low Power Tecniques
How to cite this article:

K.S.S.K. Rajesh, S. Hari Hara Subramani and V. Elamaran, 2014. CMOS VLSI Design of Low Power Comparator Logic Circuits. Asian Journal of Scientific Research, 7: 238-247.

DOI: 10.3923/ajsr.2014.238.247

URL: https://scialert.net/abstract/?doi=ajsr.2014.238.247

COMMENT ON THIS PAPER
 
 
 

 

 
 
 
 
 
 
 
 
 

 
 
 
 
 
 
 

Curve Bottom