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Journal of Applied Sciences
  Year: 2008 | Volume: 8 | Issue: 11 | Page No.: 2083-2090
DOI: 10.3923/jas.2008.2083.2090
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Parallel Circular-Scan Architecture

Mehdi Azimipour and Mohammad Eshghi

One approach to deal with today’s complicated SOCs test procedure is using scan-based designs. This serial access mechanism increases the test application time and cost. The circular-scan architecture reduces test data volume, test application time and the number of scan input counts. The basic idea of circular-scan architecture is using the captured response of the previously applied test pattern as a template for the next pattern. In this architecture, only the conflicting bits of previously captured response are updated through a data input pin. This research presents a new circular-scan architecture that makes it possible to select several scan chains in parallel. In the proposed architecture, multiple conflict bits are selected and updated simultaneously In comparison with original architecture which it is possible to select only one scan chain at each time using a regular decoder, the parallel updating of conflict bits results in more reduction in test data volume and test application time. Scan chains are selected in parallel, using a multiple-hot decoder. Experimental results show an average improvement of 26% in test data volume and test application time, in the 5 largest ISCAS'89 benchmark circuits.
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  •    Run-Length Based Efficient Compression for System-on-Chip
  •    Achieving Low Power Test Pattern By Efficient Compaction Method For SoC Design
How to cite this article:

Mehdi Azimipour and Mohammad Eshghi, 2008. Parallel Circular-Scan Architecture. Journal of Applied Sciences, 8: 2083-2090.

DOI: 10.3923/jas.2008.2083.2090






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