This study presents a new high-speed CMOS multiplier in nanotechnology.
In this research, we have evaluated the effects of reduction technology
size (from 130 to 80 nm) on power, delay and power-delay product of multipliers.
Using nanotechnology scale electronic parameters had major effect in implementing
multipliers in this research. We used HSPICE and Synopsys for simulations.
A new multiplier, which accepts a redundant multiplicand, has been planned,
simulated and compared with previous designs. A novel algorithm using
carry save adder architecture and a new full - adder has been presented.
To work at low power voltage, the pass transistor circuit that produces
the XOR and XNOR outputs has been enhanced to solve delay problem. A carry-select
adder has been implemented by using single ripple carry adder and an adder
tree circuit. This research proposes a new adder tree using the high-speed
circuits and multiplexers. Decreasing technology size with powerful design
has decreased the power by 38% in these multipliers. The latency has decreased
by almost 36% . Our design decreased transistor count by 32 %.