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Journal of Applied Sciences
  Year: 2008 | Volume: 8 | Issue: 13 | Page No.: 2468-2473
DOI: 10.3923/jas.2008.2468.2473
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A Fast CMOS Multiplier in Nanotechnology

Pooya Assadi

This study presents a new high-speed CMOS multiplier in nanotechnology. In this research, we have evaluated the effects of reduction technology size (from 130 to 80 nm) on power, delay and power-delay product of multipliers. Using nanotechnology scale electronic parameters had major effect in implementing multipliers in this research. We used HSPICE and Synopsys for simulations. A new multiplier, which accepts a redundant multiplicand, has been planned, simulated and compared with previous designs. A novel algorithm using carry save adder architecture and a new full - adder has been presented. To work at low power voltage, the pass transistor circuit that produces the XOR and XNOR outputs has been enhanced to solve delay problem. A carry-select adder has been implemented by using single ripple carry adder and an adder tree circuit. This research proposes a new adder tree using the high-speed circuits and multiplexers. Decreasing technology size with powerful design has decreased the power by 38% in these multipliers. The latency has decreased by almost 36% . Our design decreased transistor count by 32 %.
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How to cite this article:

Pooya Assadi , 2008. A Fast CMOS Multiplier in Nanotechnology. Journal of Applied Sciences, 8: 2468-2473.

DOI: 10.3923/jas.2008.2468.2473






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