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Journal of Applied Sciences
  Year: 2007 | Volume: 7 | Issue: 7 | Page No.: 958-964
DOI: 10.3923/jas.2007.958.964
 
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Sleep Transistor Sizing According to Circuit Speed, Silicon Area and Leakage Current in High-Performance Digital Circuit Modules

Ahmet Kucukkomurler and Steven L. Garverick

Abstract:
It is proposed that the power supply of key circuit modules could be gated to achieve significant reductions of leakage current, with minimal costs to circuit speed and die area in 0.25, 0.18 and 0.07 μm technologies. This study describes an extension to power supply gating using body overdrive and gate underdrive, analysis techniques to predict leakage current and performance parameters, a procedure for optimization of the sleep transistor size and simulation results that demonstrate the accuracy of the analysis and advantages of the approach. A leakage current estimation technique has been studied using the Berkeley Predictive Technology Model Parameters. An estimation technique has been verified using ISCAS85 combinational Benchmark test circuits. Finally the optimization algorithm has been verified using these same benchmark test circuits.
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How to cite this article:

Ahmet Kucukkomurler and Steven L. Garverick, 2007. Sleep Transistor Sizing According to Circuit Speed, Silicon Area and Leakage Current in High-Performance Digital Circuit Modules. Journal of Applied Sciences, 7: 958-964.

DOI: 10.3923/jas.2007.958.964

URL: https://scialert.net/abstract/?doi=jas.2007.958.964

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