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Journal of Applied Sciences

Year: 2006 | Volume: 6 | Issue: 9 | Page No.: 1978-1981
Research Article

A Novel Low Power and High Performance 14 Transistor CMOS Full Adder Cell

T. Vigneswaran
Department ofECE, SRM Engineering College, Chennai-603203, India
B. Mukundhan
Department ofECE, SRM Engineering College, Chennai-603203, India
P. Subbarami Reddy
Department ofECE, SRM Engineering College, Chennai-603203, India
Full adders are important components in applications such as Digital Signal Processors (DSP) architectures and microprocessors. Demands for the low power VLSI have been pushing the development of aggressive design methodologies to reduce the power consumption drastically. To meet the growing demand, The present study propose a new low power adder cell by sacrificing the MOS Transistor count that reduces the serious threshold loss problem, considerably increases the speed and decreases the power when compared to the Static Energy Recovery Full (SERF) adder. So a new improved 14T CMOS l-bit full adder cell is presented in the present study. Results show 50% improvement in threshold loss problem, 48% improvement in speed and considerable power consumption over the SERF adder and other different types of adders with comparable performance.
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References

  1. Ahmed, M.S. and A.M. Bayoumi, 1998. A new full adder cell for low power applications. Proceedings of the IEEE Great Lakes Symposium on VLSI, 1998, Louisiana University, pp: 45-49.
  2. Oklobdzija, V.G., M. Soderstrand and B. Duchene, 1995. Development and synthesis method for pass-transistor logic family for high speed and low power CMOS. Proceedings of the 1995 IEEE 38th Midwest Symposium Circuits Systems, 1995, Rio Janeiro, pp: 298-301.
  3. Shalem, R., E. John and L.K. John, 1999. A novel low power energy recovery full adder cell. Proceedings of the IEEE Great Lakes VLSI Symposium, 1999, Ann Arbor, MI, USA., pp: 380-380.
  4. Weste, N. and K. Eshraghian, 1993. Principles of CMOSVLSI Design a System Perspective. Reading, MA Addison Wesley, UK.
  5. Zhuang, N. and H. Wu, 1992. A new design of the CMOS full adder. IEEE J. Solid-State Circuits, 27: 840-844.
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  6. Zimmermann, R. and W. Fichtner, 1997. Low-power logic styles: CMOS versus pass-transistor logic. IEEE J. Solid-State Circ., 32: 1079-1090.
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