Research Article

FPGA Implementation of Turbo Decoder for LTE Standard

K. Kalyani, A. Sakthi Amutha Vardhini and S. Rajaram

The data rate of 100 Mbps will be supported by upcoming 3G Long Term Evolution (LTE) standard. In 20 MHZ of bandwidth, this data rate will be attained. For the arrival of high data rate of the 3G LTE systems, there is an essential requirement of turbo decoder implementation. In this work, Log-MAP algorithm based turbo decoder for LTE receiver is proposed. The Log-MAP based turbo decoder provides performance nearer to Shannon’s limit with reasonable computational complexity. The VHDL coding for parallel architecture of turbo decoder using Log-MAP algorithm for LTE is simulated and synthesized using Xilinx XC3S200-4ft256, Spartan 3 family and the results are verified with the manual calculation.

PDF Fulltext XML References Citation

How to cite this article

K. Kalyani, A. Sakthi Amutha Vardhini and S. Rajaram, 2013. FPGA Implementation of Turbo Decoder for LTE Standard. Journal of Artificial Intelligence, 6: 22-32.

DOI: 10.3923/jai.2013.22.32

URL: https://scialert.net/abstract/?doi=jai.2013.22.32

Comments

jyoti sharma Reply

06 October, 2016

this paper used for my thesis.

Journal of Artificial Intelligence

Article Trend

Total views 858

Search

Authors

K. Kalyani

A. Sakthi Amutha Vardhini

S. Rajaram

Keywords

Research Article

FPGA Implementation of Turbo Decoder for LTE Standard

How to cite this article

Comments

jyoti sharma Reply

Leave a Comment