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Information Technology Journal
  Year: 2014 | Volume: 13 | Issue: 4 | Page No.: 768-774
DOI: 10.3923/itj.2014.768.774
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Design of a New Structure of SAR ADC

JingJing Lv, Hua Chen, Yongheng Shang, LiPing Wang and Faxin Yu

This study introduces a novel design of 1MHz 8-bits Successive Approximation Analog-to-Digital Conversion (SAR ADC) circuit for the application of AGC (Auto-Gain Control) module within a RF (Radio Frequency) receiver channel by using 0.25 μm SOI CMOS (Silicon On Insulation, Complementary Metal Oxide Semiconductor) process. The schematic design of the proposed circuit is based on the R-2R resistor matching network, current mirror structure and high precision comparator. Such arrangement improves the overall precision of the proposed SAR ADC. An inside start-pulse generator is employed at the same time to achieve a compact time sequence and further improve the utilization of the overall system clock frequency. The testing results show that the DNL for the proposed SAR ADC is less than 0.5 LSB and its INL is less than 1 LSB.
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How to cite this article:

JingJing Lv, Hua Chen, Yongheng Shang, LiPing Wang and Faxin Yu, 2014. Design of a New Structure of SAR ADC. Information Technology Journal, 13: 768-774.

DOI: 10.3923/itj.2014.768.774






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