Research Article
Leakage Tolerant, Noise Immune Domino Logic for Circuit Design in the Ultra Deep Submicron CMOS Technology for High Fan-in Gates

Citation to this article as recorded by ASCI
Elamaran, V., G. Rajkumar, S.S. Rajpurohit and R.A. Krishnan, 2014. A novel low power adder-subtractor using efficient XOR gates. J. Applied Sci., 14: 1623-1627.
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Rajesh, K.S.S.K., S.H.H. Subramani and V. Elamaran, 2014. CMOS VLSI design of low power comparator logic circuits. Asian J. Sci. Res., 7: 238-247.
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Subramani, S.H.H., K.S.S.K. Rajesh and V. Elamaran, 2014. Low energy, low power adder logic cells: A CMOS VLSI implementation. Asian J. Sci. Res., 7: 248-255.
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V. Elamaran, N. Raju , Anooj Krishnan , Kalagarla Abhiram 2014. CMOS VLSI Implementation of Adders with Low Leakage Power J. Applied Sci., 14: 1550-1556.
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