Research Article

The Design and FPGA Implementation of FSM-based Intellectual Property Watermark Algorithm at Behavioral Level

Wei Liang, Xingming Sun, Zhiqiang Ruan and Jing Long

A Finite State Machine (FSM)-based Intellectual Property (IP) watermark algorithm at behavioral level is presented for the protection of IP reuse techniques in Very Large Scale Integration (VLSI). The proposed algorithm extracts the maximal delay state set through state transformation relations among circuit signals. The watermark is mapped into additional delay constraint sequence by constraint generator, and the value in the sequence is added into the maximal delay state set in the circuit for embedding watermark. The algorithm is tested on Virtex XCV600-6bg432 Field-Programmable Gate Array (FPGA), the experimental results show that the algorithms has lower impact on logical function, ensures better security and lower (resource) overhead in comparison with other methods.

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Wei Liang, Xingming Sun, Zhiqiang Ruan and Jing Long, 2011. The Design and FPGA Implementation of FSM-based Intellectual Property Watermark Algorithm at Behavioral Level. Information Technology Journal, 10: 870-876.

DOI: 10.3923/itj.2011.870.876

URL: https://scialert.net/abstract/?doi=itj.2011.870.876

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Authors

Wei Liang

Xingming Sun

Zhiqiang Ruan

Jing Long

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Research Article

The Design and FPGA Implementation of FSM-based Intellectual Property Watermark Algorithm at Behavioral Level

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