Fang-Hsi Kuo
Department of Information Management,
Jin Wen Institute of Technology, Taiwan, Republic of China
Shou-Te Yen
Computer System Laboratory,
Department of Information Engineering and Computer Science, Feng Chia University, Taiwan, Republic of China
Chia-Cheng Liu
Computer System Laboratory,
Department of Information Engineering and Computer Science, Feng Chia University, Taiwan, Republic of China
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How to cite this article
Fang-Hsi Kuo, Shou-Te Yen and Chia-Cheng Liu, 2005. A Multi-FPGA Rapid Prototyping System with the Reusable AES Core. Information Technology Journal, 4: 262-270.
DOI: 10.3923/itj.2005.262.270
URL: https://scialert.net/abstract/?doi=itj.2005.262.270
DOI: 10.3923/itj.2005.262.270
URL: https://scialert.net/abstract/?doi=itj.2005.262.270