Citation to this article as recorded by
Novel CMOS Multi-bit Counter for Speed-Power Optimization in
Multiplier Design AEU - International Journal of Electronics and Communications |
How to cite this article
C.N. Marimuthu and P. Thangaraj, 2010. Transmission Gate based High Performance Low Power Multiplier. Journal of Applied Sciences, 10: 3051-3059.
DOI: 10.3923/jas.2010.3051.3059
URL: https://scialert.net/abstract/?doi=jas.2010.3051.3059
DOI: 10.3923/jas.2010.3051.3059
URL: https://scialert.net/abstract/?doi=jas.2010.3051.3059