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Journal of Applied Sciences
  Year: 2010 | Volume: 10 | Issue: 23 | Page No.: 3051-3059
DOI: 10.3923/jas.2010.3051.3059
 
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Transmission Gate based High Performance Low Power Multiplier

C.N. Marimuthu and P. Thangaraj

Abstract:
The performance analysis of various multiplier architectures are compared in terms of power, delay and area occupation in the view of low-power low-voltage signal processing for low-frequency applications. A novel practical approach has been set up to investigate and graphically represent the mechanisms of glitch generation and propagation. It is found that spurious activity is a major source of power dissipation in multipliers. Measurements point out that the shorter full-adder chains in the Wallace multiplier dissipates less energy than as compare to other longer full-adder chains traditional array multipliers. The benefits of transistor sizing are also evaluated. In this study transmission gates combined with static CMOS circuits to reduce glitches in Wallace multiplier architecture is proposed to improve the energy-efficiency as compare to traditional array architecture. The reduced number of Vdd-to-ground paths, reduced glitches due to level restoring gates, the equalized internal signal delay and shortening of full adder chains are the unique techniques used to reduce power dissipation in proposed transmission gate based Wallace multipliers as compare to prior designs.
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How to cite this article:

C.N. Marimuthu and P. Thangaraj, 2010. Transmission Gate based High Performance Low Power Multiplier. Journal of Applied Sciences, 10: 3051-3059.

DOI: 10.3923/jas.2010.3051.3059

URL: https://scialert.net/abstract/?doi=jas.2010.3051.3059

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