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S. Saravanan and Har Narayan Upadhyay, 2012. Achieving Low Power Test Pattern By Efficient Compaction Method For SoC Design. Journal of Artificial Intelligence, 5: 244-248.
DOI: 10.3923/jai.2012.244.248
URL: https://scialert.net/abstract/?doi=jai.2012.244.248
DOI: 10.3923/jai.2012.244.248
URL: https://scialert.net/abstract/?doi=jai.2012.244.248