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Elamaran, V. and H.N. Upadhyay, 2015. Low power digital barrel shifter datapath circuits using microwind layout editor with high reliability. Asian J. Sci. Res., 8: 478-489. CrossRefDirect Link |
V. Elamaran and H.N. Upadhyay, 2015. CMOS VLSI design of low power SRAM cell architectures with new TMR: a layout approach. Asian J. Sci. Res., 8: 466-477. CrossRefDirect Link |
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How to cite this article
S. Hari Hara Subramani, K.S.S.K. Rajesh and V. Elamaran, 2014. Low Energy, Low Power Adder Logic Cells: A CMOS VLSI Implementation. Asian Journal of Scientific Research, 7: 248-255.
DOI: 10.3923/ajsr.2014.248.255
URL: https://scialert.net/abstract/?doi=ajsr.2014.248.255
DOI: 10.3923/ajsr.2014.248.255
URL: https://scialert.net/abstract/?doi=ajsr.2014.248.255