Journal of Applied Sciences1812-56541812-5662Asian Network for Scientific Information10.3923/jas.2013.197.200KirubanandasarathyN.KarthikeyanK.12013131In this study, an area-efficient low power FFT (Fast Fourier
Transform) processor is proposed for MIMO-OFDM (Multi Input Multi Output-Orthogonal
Frequency Division Multiplexing) that consists of a modified architecture of
radix-2 algorithm which is described as Radix-2 Multipath Delay Commutation
(R2MDC). Orthogonal frequency-division multiplexing is a popular method for
high-data-rate wireless transmission. OFDM may be combined with multiple antennas
at both the access point and mobile terminal to increase diversity gain and/or
Enhance system capacity on a time-varying multi path fading channel, resulting
in a multiple-input multiple-output OFDM system. This study described the VLSI
design of R2MDC FFT for high throughput MIMO OFDM transceivers targeted to future
wireless LAN systems. The proposed system is pipelined Radix 2 multipath delay
commutation FFT has been designed for MIMO OFDM. The MIMO OFDM transceivers
have been designed according to the proposed OFDM parameters. A low-power efficient
and full-pipelined architecture enables the real-time operations of MIMO OFDM
transceivers. The FPGA board has been developed to verify their circuit behavior
and implementation of MIMO OFDM Transceivers.]]>Alamouti, S.,1998Becker, J.,2002Blum, R.S., Y.G. Li, J.H. Winters and Q. Yan,2001Bolcskei, H., D. Gesbert and A.J. Paulraj,2002Coulton, P. and D. Carline,2004Dick, C. and F. Harris,2003Han, W., T. Arslan, A.T. Erdogan and M. Hasan,2005Jongren, G., M. Skoglund and B. Ottersten,2002Kirubanandasarathy, N., K. Karthikeyan and K. Thirunadanasikamani,2010Kirubanandasarathy, N. and K. Karthikeyan,2012Terry, J. and J. Heiskala,2002