Journal of Applied Sciences1812-56541812-5662Asian Network for Scientific Information10.3923/jas.2012.2172.2177AlsharefA.A. Mohd. AliM.A. SanusiH. 1220121220A new full simulation, design and verification of a Direct
Digital Frequency Synthesizer (DDFS), utilizing only one quarter of a given
sinusoidal wave, are presented in this study. A reduction in the size of the
LUT is accomplished as the new design requires storing only a quarter of the
sine wave. The Register Transfer Level (RTL) and the Gate level is implemented
by the Quartus II. The Quartus II will then invoke the ModelSim Altera software
to simulate the output. The DDFS consists of three major models, mainly a Phase
Accumulator (PA), a Phase Register and a Look Up Table (LUT). All of the mentioned
models are realized by a Verilog code. The spurious free dynamic range is achieved
with a value of -73 dB using a 16 bit phase accumulator. The proposed design
is verified through the application of different input frequencies and obtained
results showed that output frequency is directly proportional to the tuning
input frequency.]]>Vankka, J. and K. Halonen,2001Bellaouar, A., M.S. O'brecht, A.M. Fahim and M.I. Elmasry,200035385390Mortezapour, S. and E.K.F. Lee,19993413501359Sunderland, D.A., R.A. Strauch, S.S. Wharfield, H.T. Peterson and C.R. Cole,198419497506Nicholas, H., H. Samueli and B. Kim,19881988pp: 357363Hegazi, E.M., H.F. Ragaie, H. Haddara and H. Ghali,19981998pp: 647650Sharma, R.K. and G. Upadhyaya,2010217938201Wang, Q., S. He and Z. Zhong,20102010pp: 13Bramble, A.L.,19811981pp: 406414Grayver, E. and B. Daneshrad,19981998pp: 241244Vankka, J., M. Waltari, M. Kosunen and K.A.I. Halonen,199833218227Yi-Yuan, F. and C. Xue-Jun,20112011pp: 357360