Information Technology Journal1812-56381812-5646Asian Network for Scientific Information10.3923/itj.2013.6513.6518WeiCheng XiaZhang Jian-PingHu Cheng-HaoHan 1220131222The leakage dissipation catches up with the dynamic power consumption gradually and it is becoming an important factor in low-power CMOS circuits. In this work, a p-type complementary pass-transistor adiabatic logic (P-CPAL) using DTCMOS and gate-length biasing techniques is proposed. In order to reduce sub-threshold leakage dissipations, DTCMOS and gate-length biasing techniques are used for the P-CPAL circuits. An ISCAS benchmark circuit using DTCMOS and gate-length biasing techniques is verified. All circuits are simulated with HSPICE using a NCSU 65nm PTM (Predictive Technology Model) process. Results show that both leakage and dynamic dissipations of the P-CPAL circuits with dual-threshold CMOS and gate-length biasing techniques are reduced greatly compared with the normal P-CPAL circuits.]]>Hu, J.P., T.F. Xu and H. Li,2005E88-D14791485Liu, F. and K.T. Lau,199834739741Moon, Y. and D.K. Jeong,199631514522Rabaey, J.M.,1996Yu, X., X. Luo and J. Hu,20112011pp: 14Zhang, W., J. Hu and L. Yu,20111023922398