Information Technology Journal1812-56381812-5646Asian Network for Scientific Information10.3923/itj.2006.25.29Josemin BalaG .PerinbamJ. Raja Paul1200651This study presents a novel architecture for data compression using Adiabatic Logic. The Data Compression unit uses Pass transistor Adiabatic Logic (PAL) Content Addressable Memory (CAM) for pattern matching required by BSTW compression process. SPICE simulation of adiabatic compressor indicate around 50% of power saving at 10 MHZ operating frequency compared to conventional design. Circuits are designed using 0.6 μm CMOS technology.]]>Athas, W.C., L.J. Svensson, J.G. Koller, N. Tzartzanis and E.Y. Chou,19942398407Jones, S.,1992139498502Lin, K.J. and C.W. Wu,20004911391145Belle, W ., Y. Wei, R. Tarver, J.S. Kim and N.G. Kevin,19931993pp: 19531955Jones, S.,2000147329334Oklobdzija, V.G., D. Maksimovic and F. Lin,199744842846Meimand, H.M., A.A. Kusha and M. Nourani,20002000pp: 324327Athas, W.C., N. Tzartzanis, L.J. Svensson and L. Peterson,19973216931700