<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE article
  PUBLIC "-//NLM//DTD Journal Publishing DTD v2.0 20040830//EN" "http://dtd.nlm.nih.gov/publishing/2.0/journalpublishing.dtd">
<article xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:mml="http://www.w3.org/1998/Math/MathML" article-type="research-article" dtd-version="2.0" xml:lang="EN">

  <front>

    <journal-meta>

      <journal-title>Asian Journal of Scientific Research</journal-title>

      <issn pub-type="ppub">1992-1454</issn>

      <issn pub-type="epub">2077-2076</issn>

      <publisher>

        <publisher-name>Asian Network for Scientific Information</publisher-name>

      </publisher>

    </journal-meta>


    <article-meta>

      <article-id pub-id-type="doi">10.3923/ajsr.2015.478.489</article-id>


      <title-group>

        <article-title><![CDATA[Low Power Digital Barrel Shifter Datapath Circuits Using Microwind Layout Editor with High Reliability]]></article-title>

      </title-group>


      <contrib-group>

        <contrib contrib-type="author" xlink:type="simple">


          <name name-style="western">

            <surname>Elamaran</surname>

            <given-names>V.</given-names>

          </name>


          <name name-style="western">

            <surname>Upadhyay</surname>

            <given-names>Har Narayan</given-names>

          </name>


        </contrib>

      </contrib-group>


      <pub-date pub-type="collection">


        <month>4</month>




        <year>2015</year>

      </pub-date>


      <volume>8</volume>

      <issue>4</issue>


      <abstract><![CDATA[<p>Since the performance of portable electronic products increases continuously with demand, there is a need for low power digital VLSI design. Due to limited backup time of batteries, the operating time of portable electronic products is highly restricted. So, the designers now concentrate on low power rather than the speed of the device or system. We implement a 4 bit barrel shifter using different flavors like conventional CMOS logic, pass transistor logic and transmission gate logic styles. Electronic Computer Aided Design (CAD) tools like Microwind and a DSCH are used in our simulations by which the comparison of power in each style is provided. Microwind is used a layout editor and DSCH (Digital Schematic) is used as a schematic editor. Results show that the pass transistor logic consumes less power with minimum area and good performance. We used BSIM4 MOSFET model in 0.12 &mu;m for experimental results. To improve the reliability of the circuits, fault tolerant voter circuits are implemented. The results are compared with the existing approaches and the proposed methods.</p>]]></abstract>


    </article-meta>

  </front>


  <ref-list>










      <ref id="72127">

        <label>1</label>

        <citation citation-type="conference" xlink:type="simple">

          <person-group person-group-type="author">

            <name name-style="western">

              <surname>Bardizbanyan, A., K.P. Subramaniyan and P. Larsson-Edefors,</surname>

              <given-names></given-names>

            </name>

          </person-group>

          <year>2010</year>

          <article-title><![CDATA[Generation and exploration of layouts for Area-efficient barrel shifters.]]></article-title>

          <source>Proceedings of the IEEE Computer Society Annual Symposium on VLSI,</source>

          <volume>2010</volume>

          <fpage>pp: 454</fpage>

          <lpage>455</lpage>

        </citation>

      </ref>












      <ref id="1212466">

        <label>2</label>

        <citation citation-type="journal" xlink:type="simple">

          <person-group person-group-type="author">

            <name name-style="western">

              <surname>Elamaran, V. and H.N. Upadhyay,</surname>

              <given-names></given-names>

            </name>

          </person-group>

          <year>2013</year>

          <article-title><![CDATA[A case study of nanoscale FPGA programmable switches with low power.]]></article-title>

          <source>Int. J. Eng. Technol.,</source>

          <volume>5</volume>

          <fpage>1512</fpage>

          <lpage>1519</lpage>

        </citation>

      </ref>
























      <ref id="58920">

        <label>3</label>

        <citation citation-type="conference" xlink:type="simple">

          <person-group person-group-type="author">

            <name name-style="western">

              <surname>Elamaran, V., N.B.P. Reddy and K. Abhiram,</surname>

              <given-names></given-names>

            </name>

          </person-group>

          <year>2012</year>

          <article-title><![CDATA[Low power prescaler implementation in CMOS VLSI.]]></article-title>

          <source>Proceedings of the International Conference on Emerging Trends in Electrical Engineering and Energy Management,</source>

          <volume>2012</volume>

          <fpage>pp: 16</fpage>

          <lpage>19</lpage>

        </citation>

      </ref>














      <ref id="132530">

        <label>4</label>

        <citation citation-type="book" xlink:type="simple">

          <person-group person-group-type="author">

            <name name-style="western">

              <surname>Wakerly, J.F.,</surname>

              <given-names></given-names>

            </name>

          </person-group>

          <year>2008</year>

          <article-title><![CDATA[Digital Design: Principles and Practices.]]></article-title>

          <source>Digital Design: Principles and Practices.</source>

          <volume>4th Edn.,</volume>

          <fpage>Pages: 852</fpage>

          <lpage>Pages: 852</lpage>

        </citation>

      </ref>
















      <ref id="1442534">

        <label>5</label>

        <citation citation-type="journal" xlink:type="simple">

          <person-group person-group-type="author">

            <name name-style="western">

              <surname>Peng, J.J., Y.P. Liu and Y.Y. Chen,</surname>

              <given-names></given-names>

            </name>

          </person-group>

          <year>2012</year>

          <article-title><![CDATA[A dependability model for TMR system.]]></article-title>

          <source>Int. J. Autom. Comput.,</source>

          <volume>9</volume>

          <fpage>315</fpage>

          <lpage>324</lpage>

        </citation>

      </ref>
























      <ref id="72129">

        <label>6</label>

        <citation citation-type="conference" xlink:type="simple">

          <person-group person-group-type="author">

            <name name-style="western">

              <surname>Khandekar, P.D. and S. Subbaraman,</surname>

              <given-names></given-names>

            </name>

          </person-group>

          <year>2008</year>

          <article-title><![CDATA[Low power 2:1 MUX for barrel shifter.]]></article-title>

          <source>Proceedings of the 1st International Conference on Emerging Trends in Engineering and Technology,</source>

          <volume>2008</volume>

          <fpage>pp: 404</fpage>

          <lpage>407</lpage>

        </citation>

      </ref>












      <ref id="1351623">

        <label>7</label>

        <citation citation-type="journal" xlink:type="simple">

          <person-group person-group-type="author">

            <name name-style="western">

              <surname>Rajesh, K.S.S.K., S.H.H. Subramani and V. Elamaran,</surname>

              <given-names></given-names>

            </name>

          </person-group>

          <year>2014</year>

          <article-title><![CDATA[CMOS VLSI design of low power comparator logic circuits.]]></article-title>

          <source>Asian J. Sci. Res.,</source>

          <volume>7</volume>

          <fpage>238</fpage>

          <lpage>247</lpage>

        </citation>

      </ref>


















      <ref id="1182171">

        <label>8</label>

        <citation citation-type="journal" xlink:type="simple">

          <person-group person-group-type="author">

            <name name-style="western">

              <surname>Priya, M.G., K. Baskaran, D. Krishnaveni and S. Srinivasan,</surname>

              <given-names></given-names>

            </name>

          </person-group>

          <year>2012</year>

          <article-title><![CDATA[A new leakage power reduction technique for CMOS VLSI circuits.]]></article-title>

          <source>J. Artif. Intell.,</source>

          <volume>5</volume>

          <fpage>227</fpage>

          <lpage>232</lpage>

        </citation>

      </ref>




















      <ref id="132531">

        <label>9</label>

        <citation citation-type="book" xlink:type="simple">

          <person-group person-group-type="author">

            <name name-style="western">

              <surname>Lala, P.K.,</surname>

              <given-names></given-names>

            </name>

          </person-group>

          <year>2008</year>

          <article-title><![CDATA[An Introduction to Logic Circuit Testing.]]></article-title>

          <source>An Introduction to Logic Circuit Testing.</source>

          <volume> </volume>

          <fpage>Pages: 112</fpage>

          <lpage>Pages: 112</lpage>

        </citation>

      </ref>
















      <ref id="1421328">

        <label>10</label>

        <citation citation-type="journal" xlink:type="simple">

          <person-group person-group-type="author">

            <name name-style="western">

              <surname>Kshirsagar, R.V. and R.M. Patrikar,</surname>

              <given-names></given-names>

            </name>

          </person-group>

          <year>2009</year>

          <article-title><![CDATA[Design of a novel fault-tolerant voter circuit for TMR implementation to improve reliability in digital circuits.]]></article-title>

          <source>Microelectron. Reliability,</source>

          <volume>49</volume>

          <fpage>1573</fpage>

          <lpage>1577</lpage>

        </citation>

      </ref>


















      <ref id="1351624">

        <label>11</label>

        <citation citation-type="journal" xlink:type="simple">

          <person-group person-group-type="author">

            <name name-style="western">

              <surname>Subramani, S.H.H., K.S.S.K. Rajesh and V. Elamaran,</surname>

              <given-names></given-names>

            </name>

          </person-group>

          <year>2014</year>

          <article-title><![CDATA[Low energy, low power adder logic cells: A CMOS VLSI implementation.]]></article-title>

          <source>Asian J. Sci. Res.,</source>

          <volume>7</volume>

          <fpage>248</fpage>

          <lpage>255</lpage>

        </citation>

      </ref>


















      <ref id="1442544">

        <label>12</label>

        <citation citation-type="journal" xlink:type="simple">

          <person-group person-group-type="author">

            <name name-style="western">

              <surname>Govindarajulu, S., T.J. Prasad and N. Ramanjaneyulu,</surname>

              <given-names></given-names>

            </name>

          </person-group>

          <year>2010</year>

          <article-title><![CDATA[Design of high performance arithmetic and logic circuits in DSM technology.]]></article-title>

          <source>Int. J. Eng. Technol.,</source>

          <volume>2</volume>

          <fpage>285</fpage>

          <lpage>291</lpage>

        </citation>

      </ref>




















      <ref id="130659">

        <label>13</label>

        <citation citation-type="book" xlink:type="simple">

          <person-group person-group-type="author">

            <name name-style="western">

              <surname>Brown, S., S.D.M. Brown and Z.G. Vranesic,</surname>

              <given-names></given-names>

            </name>

          </person-group>

          <year>2008</year>

          <article-title><![CDATA[Fundamentals of Digital Logic with VHDL Design.]]></article-title>

          <source>Fundamentals of Digital Logic with VHDL Design.</source>

          <volume>3rd Edn.,</volume>

          <fpage>Pages: 960</fpage>

          <lpage>Pages: 960</lpage>

        </citation>

      </ref>


















      <ref id="130660">

        <label>14</label>

        <citation citation-type="book" xlink:type="simple">

          <person-group person-group-type="author">

            <name name-style="western">

              <surname>Uyemura, J.P.,</surname>

              <given-names></given-names>

            </name>

          </person-group>

          <year>2006</year>

          <article-title><![CDATA[Introduction to VLSI Circuits and Systems.]]></article-title>

          <source>Introduction to VLSI Circuits and Systems.</source>

          <volume> </volume>

          <fpage>Pages: 656</fpage>

          <lpage>Pages: 656</lpage>

        </citation>

      </ref>
















      <ref id="1348541">

        <label>15</label>

        <citation citation-type="journal" xlink:type="simple">

          <person-group person-group-type="author">

            <name name-style="western">

              <surname>Elamaran, V., G. Rajkumar, S.S. Rajpurohit and R.A. Krishnan,</surname>

              <given-names></given-names>

            </name>

          </person-group>

          <year>2014</year>

          <article-title><![CDATA[A novel low power adder-subtractor using efficient XOR gates.]]></article-title>

          <source>J. Applied Sci.,</source>

          <volume>14</volume>

          <fpage>1623</fpage>

          <lpage>1627</lpage>

        </citation>

      </ref>


















      <ref id="124589">

        <label>16</label>

        <citation citation-type="journal" xlink:type="simple">

          <person-group person-group-type="author">

            <name name-style="western">

              <surname>Vigneswaran, T., B. Mukundhan and P.S. Reddy,</surname>

              <given-names></given-names>

            </name>

          </person-group>

          <year>2006</year>

          <article-title><![CDATA[A novel low power and high performance 14 transistor CMOS full adder cell.]]></article-title>

          <source>J. Applied Sci.,</source>

          <volume>6</volume>

          <fpage>1978</fpage>

          <lpage>1981</lpage>

        </citation>

      </ref>




















      <ref id="132533">

        <label>17</label>

        <citation citation-type="book" xlink:type="simple">

          <person-group person-group-type="author">

            <name name-style="western">

              <surname>Pedroni, V.A.,</surname>

              <given-names></given-names>

            </name>

          </person-group>

          <year>2008</year>

          <article-title><![CDATA[Digital Electronics and Design with VHDL.]]></article-title>

          <source>Digital Electronics and Design with VHDL.</source>

          <volume> </volume>

          <fpage>Pages: 693</fpage>

          <lpage>Pages: 693</lpage>

        </citation>

      </ref>


















      <ref id="130662">

        <label>18</label>

        <citation citation-type="book" xlink:type="simple">

          <person-group person-group-type="author">

            <name name-style="western">

              <surname>Weste, N.H.E., D. Harris and A. Banerjee,</surname>

              <given-names></given-names>

            </name>

          </person-group>

          <year>2012</year>

          <article-title><![CDATA[CMOS VLSI Design: A Circuits and Systems Perspective.]]></article-title>

          <source>CMOS VLSI Design: A Circuits and Systems Perspective.</source>

          <volume> </volume>

          <fpage>Pages: 696</fpage>

          <lpage>Pages: 696</lpage>

        </citation>

      </ref>


















      <ref id="130663">

        <label>19</label>

        <citation citation-type="book" xlink:type="simple">

          <person-group person-group-type="author">

            <name name-style="western">

              <surname>Yeap, G.K.,</surname>

              <given-names></given-names>

            </name>

          </person-group>

          <year>2008</year>

          <article-title><![CDATA[Practical Low Power Digital VLSI Design.]]></article-title>

          <source>Practical Low Power Digital VLSI Design.</source>

          <volume> </volume>

          <fpage>Pages: 233</fpage>

          <lpage>Pages: 233</lpage>

        </citation>

      </ref>














  </ref-list>

</article>

