Research Article
High Degree of Testability Using Full Scan Chain and ATPG-An Industrial Perspective

Citation to this article as recorded by ASCI
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Balasubramaniyan, A., S. Saravanan and H.N. Upadhyay, 2013. Run-length based efficient compression for system-on-chip. J. Artif. Intel., 6: 107-111.
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Saravanan, S. and H.N. Upadhyay, 2012. Achieving low power test pattern by efficient compaction method for soc design. J. Artif. Intel., 5: 244-248.
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