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Citations for "High Degree of Testability Using Full Scan Chain and ATPG-An Industrial Perspective"


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Balasubramaniyan, A., S. Saravanan and H.N. Upadhyay, 2013. Run-length based efficient compression for system-on-chip. J. Artif. Intel., 6: 107-111.
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Saravanan, S. and H.N. Upadhyay, 2012. Achieving low power test pattern by efficient compaction method for soc design. J. Artif. Intel., 5: 244-248.
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Wang, I.C., 2012. Cost reduction in supply chain management by shorter purchasing lead-time: A case study of flexible printed circuit boards. J. Applied Sci., 12: 271-278.
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Cost Reduction in Supply Chain Management by Shorter Purchasing Lead-time: A Case Study of Flexible Printed Circuit Boards
Journal of Applied Sciences Vol. 12, Issue 3, 271, 2012

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