Abstract: Information science has undoubtedly engulfed the world. While astonishing on such growth, at the same time the invention of new protocols and procedures to guard the information have been going on in an effective way. Many of the transactions use images for sharing information. Image encryption needs a definite attention in such circumstances. In this study, FPGA based spatial image encryption has been proposed. The suggested approach uses variable key with Galois Field (GF) multiplier over 28 for encrypting the 128x128 image which was stored in internal memory of Cyclone II EP2C35F672C6 FPGA. A maximum of 11, 161 LEs (34% of total LEs) were consumed for encrypting one of the secret images Gandhiji on FPGA. This image encryption approach took 1.310 milliseconds for encrypting the 128x128 grayscale images. The effects of using fixed and variable keys for encryption have also been analyzed.
INTRODUCTION
Secure communication has attained a significant position in today’s world of rapid data transfer. Beginning from short message services offered by various telecom providers to the crucial confidential communication which happens in defense arena, the component of security finds an important assignment. Right from the initial days of internet communication, cryptography, steganography (Cheddad et al., 2010; Amirtharajan and Rayappan, 2012a-d, 2013; Amirtharajan et al., 2013a-j; Janakiraman et al., 2012a, b, 2014a, b; Luo et al., 2011; Mohammad et al., 2011; Salem et al., 2011; Ramalingam et al., 2014a, b; Thien and Lin, 2003; Zhao and Luo, 2012) and watermarking have become the warriors carrying the protection shield to guard secret information against the invaders.
Image steganography which has been employed to conceal the secret information in grayscale or RGB images has been implemented both in spatial (Chan and Chen, 2004; Amirtharajan et al., 2012; Thanikaiselvan et al., 2012a-c, 2013a, b; Wu and Tsai, 2003; Zhang and Wang, 2004; Janakiraman et al., 2012a, b, 2013; Amirtharajan and Rayappan, 2012a, c) as well as transform domains (Wong et al., 2007; Qi and Wong, 2005; Amirtharajan and Rayappan, 2012d). FPGA based and firmware based stego algorithm exist in the literature (Rajagopalan et al., 2012a, b, 2014a-d; Sundararaman and Upadhyay, 2011; Janakiraman et al., 2014a, b; Janakiraman et al., 2012c).
Due to the emergence of wireless communication technology, studies have also been suggested on secure wireless transmission of data (Thenmozhi et al., 2012; Praveenkumar et al., 2012a, b, 2013a, b, 2014a-j). Apart from textual and audio based information transfer, there is a growing option of image as a medium of information provider. Images are being used by many sections of people in daily life for sharing some important information. Those images reach out social media like facebook and have been viewed by even unauthorized people. Moreover, images related to meteorology, space and a country’s security aspects have also been communicated between the concerned in secured environment.
Image encryption is the mostly required mechanism to safeguard the images of high importance on various occasions. It has been implemented in software as well as reconfigurable hardware like FPGA platforms in the past in various related studies (Yen and Guo, 2000; Azzaz et al., 2009; Dollas et al., 2003; JianBo et al., 2009; Jridi and Alfalou, 2010; Torres-Huitzil, 2013). Scrambling, transposition, logical and arithmetic manipulations on different recursions have been performed in spatial as well as transform domain to encrypt the images. Compared to the software based approaches, hardware platforms offer a number of advantages towards the protection of secret images. Specific bit stream and hardware dependency, high speed, internal as well as external memory, IP cores etc., are some of the benefits of FPGA based image encryption approaches.
In this study, spatial domain image encryption on Cyclone II FPGA EP2C35F672C6 has been proposed. This approach mainly uses a Galois finite Field (GF) (Grossschadl, 2001) over 28 multiplier architecture for encrypting the 128x128 grayscale image stored in M4KRAM of the FPGA. Every pixel was encrypted with the help of multiplication operation between the variable encrypted key and the pixel. Cellular automata generated the new key for every pixel to be encrypted. This study also analyses the impact of using fixed and variable keys for image encryption on FPGA.
METHODOLOGY
The image encryption technique proposed in this study is based on the finite field multiplication. A field of GF over 28 has been considered as the grayscale value of pixels range between [0, 255]. GF deals with numbers which are finite in nature and various manipulations result in the values which lie in the same field. Various arithmetic and trigonometric computations have been performed in finite fields. Galois field multipliers are being used extensively in coding theory and cryptography and various such studies have been reported. The popular elliptic curve cryptography uses Galois field multipliers as a part of the computation. Let A and B be two 8-bit values where {A,B}∈{0,255}. The multiplication of A and B in Galois field has been performed as follows.
Let A = 23h = 0010 00112 and B = AAh = 1010 10102 be the 8-bit numbers. The Galois field products of these two numbers take 8 iterations. The GF multiplier uses logical AND, Galois field addition, left shift and subtraction with irreducible polynomial as main operations during the course of multiplication. As a main step, the multiplicand A will be ANDed with multiplier bit B(i), where iε{0,7} during every iteration. The resultant bits of the AND operation will be XORed with the left shifted previous iteration result. If the left shift operation yields a value which exceeds 8-bit i.e., if MSB is 1 for the 9-bit value, the XORed value will be subtracted with a irreducible polynomial x8+x4+x3+x+1 the binary equivalent of which is 100011011. The subtraction and addition operations in Galois field are performed by XOR operation.
The Galois filed multiplication of 23 and AA will be computed as follows in eight iterations:
00000000+1 (00100011) = 00000000+00100011 = 00100011
00100011+0 (00100011) = 01000110+00000000 = 01000110
In the above second iteration, before Galois field addition the addend 00100011 has been left shifted by one bit and it becomes 01000110. In the same way, the left shift operation of addend precedes the Galois field addition (i.e.,) XOR in the remaining iterations. Also, in this iteration the second bit of B (i.e.,) ‘0’ has been ANDed with all the bits of A:
01000110 + 1 (00100011) = 10001100 + 00100011 = 10101111
10101111 + 0 (00100011) = 101011110 + 000000000 = 101011110
In this fourth iteration, the addition resulted in 9-bit value. In this Galois field multiplication, left shifting the addend will not remove the MSB’s which are ‘1’ rather the resultant value becomes 9-bit with a ‘0’ added at the LSB. For the next iteration this 9-bit has to be reduced to 8-bit with the help of irreducible polynomial x8+x4+x3+x+1. Subtracting the binary equivalent of the polynomial with the 9-bit value 101011110 we get:
100011011-101011110 = 001000101
Here, subtraction has been done by XOR operation.
By neglecting the MSB ‘0’, the new 8-bit value of fourth iteration is 01000101. Moving to next iteration:
01000101+1(00100011) = 10001010+00100011 = 10101001
10101001+0(00100011) = 101010010+000000000 = 101010010
Here, again the sixth iteration produces a 9-bit value. Reducing by subtraction with irreducible polynomial we get:
100011011-101010010 = 001001001
The new sixth iteration value is 01001001. Performing the seventh iteration:
01001001+1(00100011) = 10010010+00100011 = 10110001
10110001+0(00100011) = 101100010+000000000 = 101100010
Again subtracting the obtained 9-bit result 101100010 with the polynomial:
100011011-101100010 = 001111001
The final product result of the GF multiplication between 23 and AA is 01111001 (i.e.,) 79 h. This result has been shown in Fig. 1 which displays the model_sim simulation results of 8-bit GF multiplication between AA and four 8-bit values 23, 5F, B7 and FF. The encrypt array contains the product of the four operations {79 h, 31 h, EFh, EBh}. The verification of the product was done by log table and exponential look up tables given in (XILINX, 2003). The computation with the look up tables is as follows:
| Fig. 1: | Modelsim simulation results of a 8-bit GF multiplier array |
| (1) |
| (2) |
From the logarithmic LUTs:
log GF(28) (A) = log GF(28) (23h) = B5h
log GF(28) (B) = log GF(28) (AAh) = 1Fh
From the exponential LUT:
e (log GF(28) (A.B)) = e (log GF(28) (A))+e (log GF(28) (B)) = eD4h = 79h
The proposed image encryption on 128x128 grayscale image has been performed by successive Galois multiplication of the pixel values and the modified key values. The key was initially kept fixed and GF multiplication of the entire pixels were carried out with the same key. As another approach, 8-bit pseudorandom keys were generated with 8-bit Cellular Automata (CA) R90-R90-R150-R90-R150-R90-R150-R90 (Nandi et al., 1994; Eslami et al., 2010; Wolfram, 1983). These keys were XORed and XNORed with the current pixel value to be encrypted in alternate clock cycles before multiplying with the pixel values of the secret image. The variable key approach resulted in better encryption compared to the fixed key approach which has been discussed in results and analysis section.
FPGA IMPLEMENTATION
The suggested image encryption approach was implemented in Cyclone II FPGA with various secret images of size 128x128. Initially an 8-bit GF multiplier was implemented using VHDL code and compiled in Quartus II ISE. Table 1 shows the logic elements consumption for an 8-bit GF multiplier on cyclone II FPGA. The multiplier took just one clock cycle of 50 MHz clock for computation which was achieved by employing process variables for quicker updation of results in every iteration. The multiplier took only 61 LEs out of 33,216 LEs.
The proposed encryption mechanism was implemented on five secret images Gandhiji, cameraman, house, pepper and SASTRA logo. These secret images are shown in Fig. 2(a-e). The encrypted images were stored in the internal M4KRAM of cyclone II FPGA.
| Fig. 2(a-e): | Secret images (a) Gandhiji, (b) Cameraman, (c) House, (d) Pepper and (e) SASTRA logo |
| Table 1: | Hardware consumption of 8-bit GF multiplier |
| Table 2: | Synthesis report for various images for fixed key approach |
| Table 3: | Synthesis report for various images for variable key approach |
A section of internal memory having the encrypted Gandhiji image has been shown in Fig. 3. Figure 4 displays a cross section of technology schematic of image encryption algorithm.
The logic elements consumption has been shown in Table 2 and 3 for fixed and variable key approaches. The variable key based encryption approach consumes more logic elements compared to the fixed key approach. The variable key approach has an additional component of 8-bit cellular automata for PRPG and XOR and XNOR operations performed before GF multiplication. Comparing the test images considered, minimum of 7,831 LEs were taken by SASTRA logo image with fixed key approach while the variable key method consumed 7,888 LEs.
| Fig. 3: | FPGA internal memory with encrypted Gandhiji image |
The Gandhiji image took 11,107 LEs (34%) in the fixed key approach with the same image consuming 11,161 LEs for variable key approach. Even though, there was no change the memory consumption, the fixed key approach consumed 178 registers but variable key based encryption method used 194 registers for implementing the image encryption on FPGA.
Timing analysis: The fixed as well as variable key encryption approaches have been implemented on Cyclone II FPGA with 50 MHz clock.
For fixed key approach:
| • | No. of clock cycles needed for reading new pixel value = 1 |
| • | No. of clock cycles needed for GF multiplication of pixel and fixed 8-bit key = 1 |
| • | No. of clock cycles needed for writing the encrypted pixel in M4KRAM = 1 |
| • | Total No. of pixels = 16384 |
| • | Total clock cycles needed for encrypting the 128x128 image = 16384x3 = 49152 |
| • | Total time needed for encryption = 49152x20 ns = 983.040 μs |
| Fig. 4: | Technology schematic cross section of variable key based encryption approach |
For variable key approach:
| • | No. of clock cycles needed for new 8-bit key generation with CA = 1 |
| • | No. of clock cycles needed for reading new pixel value and XOR/XNOR with key = 1 |
| • | No. of clock cycles needed for GF multiplication of pixel and variable 8-bit key = 1 |
| • | No. of clock cycles needed for writing the encrypted pixel in M4KRAM = 1 |
| • | Total No. of pixels = 16384 |
| • | Total clock cycles needed for encrypting the 128x128 image = 16384x4 = 65536 |
| • | Total time taken for encryption = 65536x20 ns = 1310.720 μs |
RESULTS AND ANALYSIS
Table 4 and 5 show the error metrics in the form of MSE and PSNR of encrypted images under fixed key and variable key approach.
Figure 5a-e show the histogram reports of various secret images considered in this image encryption algorithm. The fixed key approach uses the same 8-bit key for encrypting the entire pixels of grayscale images. This provides a problem in generating the encrypted images of high complexity. Because, if the secret image consists of maximum background or same grayscale repeated in most part of the images, the encrypted image will have same grayscale level in those areas of image. This is visible in Fig. 6e SASTRA logo image encrypted with fixed key approach. The histogram of SASTRA logo secret image also has two peaks in its report which reveals that the image has few grayscale values dominant. Figure 6a-e show the encrypted images with fixed key methodology of image encryption. Except Gandhiji and pepper images, the encryption quality was not good in cameraman, house and SASTRA logo images. Figure 7a-e show the corresponding histogram of encrypted images. It is also clear that the histogram is not uniform for all the images. In order to ensure high complexity and a strong reply to the attacks, the histogram uniformity is most important.
The second approach of variable key encryption mechanism solves this problem. As per this approach, the key changes during every new pixel taken for encryption and as a strong measure in alternate pixels XOR and XNOR operations were performed with the new pixel value before GF multiplication. Figure 8a-e show the encrypted images with variable key and their corresponding histogram have been presented in Fig. 9a-e. Now histogram plots look similar for all the five test images which shows the complexity of the variable key approach.
Table 6 and 7 show the horizontal, vertical and diagonal correlation of secret and encrypted images with fixed and variable key approaches. The correlation of pixels after encryption were very minimum compared to the secret image pixels. This statistical analysis shows the strength of the proposed image encryption on FPGA. The correlation coefficients of variable key approach were more close to 0 compared to the fixed key approach.
| Table 4: | MSE and PSNR results of the encrypted images for fixed key approach |
| Table 5: | MSE and PSNR results of the encrypted images for variable key approach |
| Table 6: | Correlation coefficients of adjacent pixels of secret images |
| Table 7: | Correlation coefficients of adjacent pixels of encrypted images with fixed and variable keys |
| Fig. 5(a-e): | Histogram of secret images (a) Gandhiji, (b) Cameraman, (c) House, (d) Pepper and (e) SASTRA logo |
| Fig. 6(a-e): | Encrypted images with single key (a) Gandhiji, (b) Cameraman, (c) House, (d) Pepper and (e) SASTRA logo |
| Fig. 7(a-e): | Histogram of encrypted images single key (a) Gandhiji, (b) Cameraman, (c) House, (d) Pepper and (e) SASTRA logo |
| Fig. 8(a-e): | Encrypted images with multiple keys (a) Gandhiji, (b) Cameraman, (c) House, (d) Pepper and (e) SASTRA logo |
| Fig. 9(a-e): | Histogram of encrypted images with multiple keys (a) Gandhiji, (b) Cameraman, (c) House, (d) Pepper and (e) SASTRA logo |
| Fig. 10(a-c): | Correlation of pixels in secret image Gandhiji (a) Horizontal, (b) Vertical and (c) Diagonal |
| Fig. 11(a-c): | Correlation of pixels in fixed key encrypted image Gandhiji (a) Horizontal, (b) Vertical and (c) Diagonalal |
| Fig. 12(a-c): | Correlation of pixels in variable key encrypted image Gandhiji (a) Horizontal, (b) Vertical and (c) Diagonal |
Figure 10-12 show the correlation images of 2000 randomly selected pixels of Gandhiji secret and encrypted images. The distribution of pixels after encryption is widespread and is visible in the correlation images.
CONCLUSION
A variable key based spatial image encryption on Cyclone II FPGA has been proposed in this study. The approach uses Galois field multiplication and cellular automata combination for providing the encryption of pixels of 128x128 grayscale images. The limitation of fixed key approach has also been discussed in this study. The proposed system can be a standalone image encryption chip which will improve the security of image sharing over the existing image encryption schemes by its specific bit stream dependency.
ACKNOWLEDGMENT
The authors wish to acknowledge SASTRA University for providing infrastructural support to carry out this study.