Abstract: There is a growing demand for techniques which improve the secure transmission of images of high confidentiality. The images captured by satellites and defense sensitive images handled by scientists need a strong protection when they are to be communicated for various applications. Image encryption algorithms need to be stronger in such cases. Various FPGA based image encryption algorithms have been proposed in the past to tighten the information security. This study analyses the hardware consumption issues of various 128x128 grayscale images which were encrypted with cellular automata circuits on Cyclone II EP2C35F672C6 FPGA. It was observed that the Logic Elements (LE) consumption varied for different test images considered in this encryption approach. This study analyses the performance of the image encryption algorithm on 15 different grayscale images based on technology schematic net lists, LE consumption, error metrics, Fast Fourier transform and histogram.
INTRODUCTION
Communication technology has seen its various incarnations over the years. It has created revolution and took the entire world by storm by means of making the once difficult thing to a door step item. However, be it personal communication or official communication, the one component which remains mandatory is security. Secure communication is the one which everyone is looking for. To counterattack the threats majorly posed by the hackers, various algorithms and approaches have been invented in the past and still the search is going on. The famous three forms of security providers are cryptography, Steganography (Cheddad et al., 2010; Amirtharajan and Rayappan, 2012a-d, 2013; Amirtharajan et al., 2012, 2013a-j; Janakiraman et al., 2012a, b, 2014a, b; Luo et al., 2011; Ramalingam et al., 2014a; Mohammad et al., 2011; Salem et al., 2011; Thien and Lin, 2003; Zhao and Luo, 2012) and watermarking. While the scrambling of the secret message is the job of cryptography (Ramalingam et al., 2014b), steganography conceals the information to be protected in a fictious cover which are mostly images, audio and video as other mediums using spatial (Chan and Cheng, 2004; Amirtharajan and Rayappan, 2012a; Thanikaiselvan et al., 2012a-c, 2013a, b; Wu and Tsai, 2003; Zhang and Wang, 2004; Janakiraman et al., 2012a, b, 2013; Amirtharajan and Rayappan, 2012a, c) as well as transform domain techniques (Wong et al., 2007; Qi and Wong, 2005; Amirtharajan and Rayappan, 2012d). Copyright protection of electronic documents is being performed by a process called watermarking. Steganography has been implemented in software as well as hardware platforms (Rajagopalan et al., 2012a, b, 2014a-d; Sundararaman and Upadhyay, 2011; Janakiraman et al., 2012c, 2014a, b) and various related works have been reported in the past. Due to the advancements in wireless communication, approaches for secure wireless transmission have also been suggested (Thenmozhi et al., 2012; Praveenkumar et al., 2012a, b, 2013a, b, 2014a-l).
Images have become important in everyones life. While personal image sharing happens in a large scale everyday through internet, the protection of the images occupies the center stage. Also various highly confidential images related to object, place etc., are being communicated between scientists and higher authorities which require utmost protection. Image encryption can play a pivotal role in secret transmission of images between the concerned. Image encryption has been implemented using software as well as hardware platforms (Yen and Guo, 2000; Azzaz et al., 2009; Dollas et al., 2003; JianBo et al., 2009; Jridi and Alfalou, 2010) in the different studies reported in the literature.
Image encryption on reconfigurable hardware like FPGA (Torres-Huitzil, 2013) requires some special attention. The encrypted bit stream of a specific FPGA carries the image to be protected. This is an important advantage where the confidential image can be retrieved only if a specific FPGA has been programmed with the specific bitstream. This study analyses the hardware implementation issues related to a cellular automata based image encryption technique. A 14-bit cellular automata was used to shuffle and encrypt the 128x128 grayscale image on Cyclone II EP2C35F672C6 FPGA. This study also focuses on analysis of logic elements utilization by various images while doing encryption.
METHODOLOGY
The image encryption proposed in this study deals with shuffling and encryption of the grayscale images using a 14-bit Cellular Automata (CA) with the rule combination R150-R90-R90-R90-R90-R90-R150-R90-R90-R90-R90-R90-R90-R150, where R90 and R150 represent rule 90 and rule 150, respectively. Cellular automata are pseudorandom pattern generators (Nandi et al., 1994) which consist of collection of cells or in hardware systems Flip-Flops. Cellular automata exhibits excellent pseudo randomness which produces the patterns with very minimum bit shifting in successive patterns. A maximum length sequence of 2n-1 can be generated by constructing the CA with rule 90 and 150 (Eslami et al., 2010; Wolfram, 1983). As per rule 90, the XOR operation between previous and next cell states of current time step decides the present cell status of next time step. The XOR operation between previous, present and next cell states of current time step decides the present cell status of next time step in rule 150. The 14-bit CA considered in the proposed algorithm is shown in Fig. 1.
This image encryption method uses the same 14-bit CA for performing shuffling and encryption. The 14-bit CA pattern was used as internal memory address where the new pixel value has to be stored in FPGA. Also the encryption was implemented by XORing the least 8-bits of every newly generated 14-bit CA value with the new pixel value. The proposed image encryption of a 128x128 grayscale image was implemented on Cyclone II FPGA EP2C35F672C6 with Quartus II version 7.2 ISE. The pseudo code of the proposed algorithm is given as follows:
Fig. 1: | A 14-bit CA circuit with the combination R150-R90-R90-R90-R90-R90-R150-R90-R90-R90-R90-R90-R90-R150 |
HARDWARE CONSUMPTION ANALYSIS
The CA based encryption approach was tested on 15 different secret images. The secret images are shown in Fig. 2a-o.
The histogram reports of secret images have been shown in Fig. 3a-o.
In order to understand the frequency variation of pixels in the secret images, FFT of secret images were computed using LabVIEW software. These FFT resultant images of corresponding secret images have been shown in Fig. 4a-o.
Figure 5a-o show the encrypted images, Fig. 6a-o display the histogram reports of encrypted images and Fig. 7a-o display the FFT of the encrypted images. The histogram report of the encrypted images look similar which indicates the complexity of encryption. The FFT of the encrypted images also look almost similar. This shows the uniformity in the frequency variation of encrypted images.
After encryption, the pixels of 128x128 grayscale image were stored in internal M4KRAM of Cyclone II FPGA. Table 1 shows the hardware consumption of 15 different images considered here. The Cyclone II FPGA EP2C35F672C6 which has been used for implementing this image encryption algorithm has 33,216 logic elements and 4,83,840 bits on internal RAM. All the 15 images consumed 167 registers and 1,31,072 bits for storing 128x128 grayscale image inside the FPGA during the encryption. But there was a difference in the usage of combinational functions. Of the 15 different images used in this algorithm, the maximum number of combinational functions were utilized by the 13th image in Table 1 (i.e.,) rice which used 11,781 functions. For encrypting the rice image, 11,798 LEs (36% of total LEs) have been utilized which is the maximum consumption compared to the other secret images.
Fig. 2(a-o): | Secret images of (a) Baby, (b) Barb, (c) Boat, (d) Building, (e) Cameraman, (f) Circles, (g) Coins, (h) Jet1, (i) Jet2, (j) Lena, (k) Peppers, (l) Pout, (m) Rice, (n) SASTRA logo and (o) Tyre |
Table 1: | Logic elements consumption for the proposed approach |
Similarly the test image circles consumed only 5,115 combinational functions and thereby utilizing 5,132 LEs (just 15% of the total LEs). While doing comparison between these two extremes, it was clear that even though the total memory bits usage looked same, the properties of an image was a deciding factor in the netlist creation and LE consumption. When setting 10,000 as the threshold for logic elements consumption among these 15 images, there were 6 images that consumed less than 10,000 and remaining 9 images utilized greater than 10,000 LEs.
Fig. 3(a-o): | Histograms of secret images of (a) Baby, (b) Barb, (c) Boat, (d) Building, (e) Cameraman, (f) Circles, (g) Coins, (h) Jet1, (i) Jet2, (j) Lena, (k) Peppers, (l) Pout, (m) Rice, (n) SASTRA logo and (o) Tyre |
Table 2 displays the error metrics MSE and PSNR of the secret and encrypted images. Figure 8 shows the snapshot of a section of LabVIEW block diagram used to plot FFT of the secret and encrypted images and error metrics calculation.
Let us consider the two images Rice and Circles which consumed 36 and 15% of the total LEs, respectively. The histogram of Rice image has been shown in Fig. 3m and that of Circles image has been displayed in Fig. 3f. The centralized grayscale distribution of pixels is apparently visible in the histogram of Rice image whereas the histogram of Circles image reveals the presence of very less number of mid range pixels i.e., approximately between the grayscale values 25 and 237.
Fig. 4(a-o): | FFT of secret images of (a) Baby, (b) Barb, (c) Boat, (d) Building, (e) Cameraman, (f) Circles, (g) Coins, (h) Jet1, (I) Jet2, (j) Lena, (k) Peppers, (l) Pout, (m) Rice, (n) SASTRA logo and (o) Tyre |
As per the histogram report obtained from the LabVIEW, the minimal grayscale value in rice image was 34 and the maximum was 226. But for Circles image, the minimum grayscale value was 0 and maximum being 255. Also the Circles image contains 6913 pixels having a grayscale value 0 and 2532 pixels having a grayscale value of 255. Figure 9 shows the chip planner view of the image encryption of tyre image on FPGA.
Table 3 shows the detailed resource usage summary of the image encryption of rice and circles image. The parameters in the Table 3 depict the netlist elements present in the technology schematics generated during the synthesis and compilation of the image encryption algorithms carried out on both the images.
Fig. 5(a-o): | Encrypted images of (a) Baby, (b) Barb, (c) Boat, (d) Building, (e) Cameraman, (f) Circles, (g) Coins, (h) Jet1, (i) Jet2, (j) Lena, (k) Peppers, (l) Pout, (m) Rice, (n) SASTRA logo and (o) Tyre |
Table 2: | MSE and PSNR results of the encrypted images |
Fig. 6(a-o): | Histograms of encrypted images of (a) Baby, (b) Barb, (c) Boat, (d) Building, (e) Cameraman, (f) Circles, (g) Coins, (h) Jet1, (i) Jet2, (j) Lena, (k) Peppers, (l) Pout, (m) Rice, (n) SASTRA logo and (o) Tyre |
Fig. 7(a-o): | FFT of encrypted images of (a) Baby, (b) Barb, (c) Boat, (d) Building, (e) Cameraman, (f) Circles, (g) Coins, (h) Jet1, (I) Jet2, (j) Lena, (k) Peppers, (l) Pout, (m) Rice, (n) SASTRA logo and (o) Tyre |
Table 3: | Analysis and synthesis resource usage in technology schematics |
Fig. 8: | Section of LabVIEW block diagram for performing analysis and error metrics calculation |
Fig. 9: | Chip planner view of the encryption of 128x128 tyre image |
Due to the presence of various grayscale levels between 25 and 237, the number of four-input functions were 11,180 in Rice image. These combinational functions were mainly required to perform the XOR operation between the grayscale value and 14-bit CA value during every clock cycle of execution. But for Circles image which has 6913 pixels in 0 gray level and 2532 pixels in 255 grayscale levels, the logic elements have been optimally used where only 4527 four-input functions were taken by the algorithm during the synthesis and compilation process. Similarly the other 13 images consumed different logic elements based on the grayscale dominance and distribution throughout the pixels of the images.
ACKNOWLEDGMENT
The authors wish to acknowledge SASTRA University for providing infrastructural support to carry out this research study.