Abstract: One year’s seeds, seven year's weeds’ is precisely pointed out by the proverb to highlight the importance of doing things, not too late. Even though, this Anglo Saxon work ethic is directed towards the must attitude for workmanship, the importance of this proverb for information security is phenomenal. Secure information sharing needs novel ideas and techniques to impede the incoming threats of secret drop outs. Steganography, an information hiding approach has seen a variety of flavours in terms of domains, algorithms, platforms etc. We present an information hiding approach on hardware platform where Field Programmable Gate Array (FPGA) works out a spatial domain steganographic module with fixed k-bit embedding and adaptive picture element position p where -1<P<4 and gray scale change factor C falling between 0<C<3. This stego algorithm on programmable logic hides the secret message bits in the cover image stored in External SRAM through a convolution encoder which employs a triple XOR logic for encoded message creation to enhance the imperceptibility with higher embedding capacity.
INTRODUCTION
In today’s scenario of fast paced communication and technology, where the exchange of information over the internet in the physical digital forms like video, audio image files etc has (Cheddad et al., 2010) ease of access to and is on the rise and thus, there is a dire need for high security (Petitcolas et al., 1999; Bender et al., 1996) of the scrutinized data. Hence, in this modern era, to cater to the impediment of authorization and potential hacking, Steganography (Provos and Honeyman, 2003; Zaidan et al., 2010) has gained a predominant stand in the realm of information security which revolves around factors like confidentiality, integrity. Steganography (Rabah, 2004) is a state-of-the-art terminology for hiding the clandestine information in a cover without any visible amendments to the cover. While Cryptography (Xia et al., 2009; Janakiraman et al., 2012c) encloses a key and scrambled data in its transmission, Steganography makes the very existence of the covert data is unperceivable. Of late, many techniques in steganography have been developed.
However, image steganography (Hmood et al., 2010; Amirtharajan and Rayappan 2012a, b, c, d) can be categorized into two namely: transform domain and spatial domain. While in the spatial domain, the clandestine data is hidden in the cover pixel using numerous methodologies like the least significant bit; pixel value indicator and pixel differencing, in transform domain technique, the cover pixel is primarily altered into other domains like the wavelet (Thanikaiselvan et al., 2011b) or frequency domain (Kumar et al., 2011) in which the covert data is then embedded in the corresponding cover pixel. However, spatial domain technique’s (Amirtharajan and Rayappan, 2011) utility lies mainly in its improved embedding capacity and payload as compared to the transform domain’s high robustness.
On a further note, steganography employed in spatial and transform domain could be carried out in raster or random scan (Amirtharajan and Balaguru, 2009; Amirtharajan and Rayappan, 2011; Amirtharajan et al., 2012). Even though software methodologies may work on both spatial (Padmaa et al., 2011) as well as transform domain, Steganography proposes multifarious data embedding techniques especially on hardware platform (Rajagopalan et al., 2012b) comprising of various advantages such as high speed embedding, embedding capacity, imperceptibility, specific hardware dependency etc. (Janakiraman et al., 2012b). Furthermore, a broad classification on image steganography can be performed on the basis of the methodologies implemented viz. distortion, spread spectrum (Thenmozhi et al., 2012), Transform (Thanikaiselvan et al., 2011a), substitution (Thanikaiselvan et al., 2011b), statistical (Qin et al., 2009) and cover generation methods.
RELATED WORKS
A secure spatial domain based steganography technique has been proposed by Ali et al. (2011) which cater to embed two least significant bits of covert information in a cover pixel, by transforming one bit from a one bit plane into another. However, the message which is embedded in a pixel is located in the second least significant bit or fourth least significant bit apart from the least significant bit (Mielikainen, 2006). The alterations so implemented in the cover pixel yields in a new stego pixel. In order to extract the clandestine data from the stego pixel, the author has premeditated upon a (3, 1) convolution decoder.
A mathematical formulae approach for embedding and retrieving by implementing simple LSB (least significant bit) has been propounded (Chan and Cheng, 2004). Further, it is also ascertained that there is a fair chance in reducing the Mean squared error (MSE) from 2k to 2k -1.
St = Cv- mod (Cv, 2k)+D where St is stego object (image), Cv is the cover object (image) and D is the decimal equivalent of the secret data to be hidden. Here, the extraction is also minimal: C = mod(S, 2k).
LFSR based hardware steganography proposed (Sundararaman and Upadhyay, 2011) utilizes various LFSRs as address generators to perform secret concealment on image. A quad block guided steganography on chip architecture implemented on Cyclone II FPGA with a detailed analysis has been propounded (Rajagopalan et al., 2012a). Further, the RISC processor chosen for their execution is the LPC 2136 which encloses in its core the ARM7TDMI-S having 32KB of on-chip SRAM which suffices amasses a maximum image size 128x128.
In image steganography based methodology (Janakiraman et al., 2011) smart bit manipulation of embedding the covert pixels in the lower nibble of the cover pixel has been proposed which involves the convolution encoder to embed three bits by altering utmost two bits of the cover pixel and thus, enhancing the robustness of three bit embedding. In yet another similar approach by Janakiraman et al. (2012a), efforts were taken using the modified convolution encoder to embed 4 bits of information in each pixel with a constrain to adjust not more than two bits in cover pixel to produce the stego pixel.
In present study, a secure and stable method has been proposed on the basis of a block based image steganography algorithm with its implementation in the Cyclone II EP2C20F484C7 FPGA in order to sensitize the creditability and performance of the stego based system. This image steganography (Xia et al., 2009) architecture inherits embedding of data block by block (Thien and Lin, 2003; Lu et al., 2009; Rajagopalan et al., 2012a) in a cover image divided into 4x4 blocks that is stored in external SRAM attached to reconfigurable hardware. A few objectives of this research are to perform extensive timing analysis, hardware consumption for data embedding and error metrics computation after implementation. This proposed methodology makes an optimistic effort to emphasize on the uniqueness to embed three data bits concurrently in two cover pixels and thereby, improving the randomness while embedding, by implementing convolution encoder and decoder for the process of embedding and retrieving. Hence, an aggressor would take long time to premeditate upon method to break the system.
PROPOSED METHODOLOGY
The main purpose of this paper is to improve the previous stated works in a way to provide an increased working efficiency by utilizing the advantage of con-current execution of embedding. This also aims in providing an alternative to the above mentioned method of sequential encoding to block encoding. The two major aspects involved in this study are:
| • | Embedding process based on the convolution encoder |
| • | The hardware implementation carried out using the Cyclone II FPGA EP2C20F484C7. The LSB substitution done by using the convolution encoder allows for a maximum change in the lower nibble of the cover pixel by 2 bit and enabling the capacity of 3 bit embedding into the lower nibble. This method involves a change in either one of the 4 lower bits or a combination of 2 of the lower bits. The circuit of the convolution encoder is shown in Fig. 1 |
The circuit in Fig. 1 works in a way so as to produce a new Stego image by altering the pixel value of the cover image. The input of the encoder is the lower nibble of the cover image (c4 c3 c2 c1) which produces an output (n1 n2 n3) through XOR operation as depicted in the figure.
The secret message bits (m1 m2 m3) to be embedded are compared with the decoded output and the decoder performs the changes in the cover pixel as shown below in the Table 1. Our approach travels on two variables namely P and C.
| Fig. 1: | Convolution encoder (3, 1) |
| Table 1: | Sample encoder output Vs greyscale change in cover pixel |
| No change when (N1 N2 N3) = mL m2 m3 | |
Let Cn = [b7 b6 b5 b4 b3 b2 b1 b0], Where Cn is the nth cover pixel and b7…b0 indicating the bits of cover pixel. The Picture element position variable P, which is adaptive in nature lies in the range -1<P<4, where 0 represents the LSB of a cover pixel (b0) and 3 representing the 3rd bit position from LSB (b3). The gray scale change factor C, which is given by 0<C<3, denoting the number of bits altered in the lower nibble of the cover pixel so as to generate stego pixel.
The retrieval procedure possesses a great challenge to detect the secret data. This is attributed due to the complexity involved in the decoder circuit as described. The recovery of the secret message is done by introducing a convolution decoder without a decision device at the end and simply obtaining the result. A grayscale image (128x128) is taken as a cover image. Thus, it has (128x128x8) bits that can be grouped into 1024 blocks of 4x4 matrixes that contain 16 bytes each. The pixels of the cover image thus arranged in blocks are arranged consecutively from left to right in every row. In this way, the message embedding is ensured in a block-wise manner rather than sequentially.
FPGA IMPLEMENTATION
The proposed convolution encoder based spatial domain stego system has been implemented on Cyclone II FPGA. Initially the gray scale cover Image of size 128x128 is stored in external high speed asynchronous CMOS static RAM IS61LV25616 which has 218 locations with each location capable of storing two bytes of data. A total of 16384 locations are needed to store both cover and stego images of size 128x128. Starting from location 1 to 8192 the cover image has been stored. This encoder based embedding algorithm has been implemented using a clock frequency of 100 MHZ, which is derived through PLL with a multiplication factor of 2 from the source of 50 MHZ external clock connected to FPGA. The hardware architecture is shown in Fig. 2.
The embedding process follows a continuous state machine, with five states per cycle. A state machine cycle performs the operations needed to read the cover image pixels in a SRAM location and to store back the stego pixels in external SRAM. The state machine cycle has six states namely Address, Secret, Triple XOR, Encode and Write. The state machine is shown in Fig. 3.
| Fig. 2: | Hardware architecture for CCS algorithm in FPGA |
| Fig. 3: | State Machine structure for CCS on cyclone II FPGA |
The description of each state is as follows:
| State 1: | Address: When storing the cover image on SRAM, the cover image has been stored in blocks. This means that the 128x128 cover image divided into 1024 4x4 blocks has been stored block wise continuously. For storing one 4x4 block 8 locations of SRAM is needed. The blocks are stored row wise (i.e.) first row 64 4x4 blocks find their place first and followed by next row 4x4 blocks and so on. The Address of SRAM is 18 bit data which is incremented with a counter starting from 1 to 8192 during each state machine cycle. This address state takes one clock cycle during which the Write Enable (WE) will be held at Logic High in order to read the two pixels as data bits width is 16 |
| State 2: | Secret: This state needs one clock cycle to select the embedding bits stored in FPGA registers. A total of 3 bits are required/pixel. Since we attempt to embed data in two pixels parallel, two 3-bit registers have been used to select and store the secret bits to be embedded. At the same time the data lines will be kept in high impedance state so that the two pixels in specified location will be transferred to 8-bit registers in FPGA namely a1 and a2. The pixels were transferred in such a way that a1 <= Lower Byte (location n) and a2 <= Upper Byte (location n) |
| State 3: | Triple XOR state: During this third state the convolution encoder logic has been implemented on the two lower nibbles of the two pixels read from SRAM. The following bit wise operations will be performed in one clock cycle: |
where, n1 (1), n1 (2) and n1 (3) generate the encoded bits using lower byte and n2 (1), n2 (2) and n2 (3) represent the encoded output using upper byte.
| State 4: | Encode: The output of the convolution circuit is compared with the three bit message input to be embedded on conditional basis in this state. It works in such a way that there will be an alteration in the lower nibble of the cover pixel which when passed through the circuit yields the same three bit message data. The conditions are grouped on the basis of the similarity in the alteration of the lower nibble of the cover pixels resulting in the three bit message data. Also during this state the lower nibble and upper nibble of the two pixels will be joined and stored in separate registers |
| State 5: | Write: The stego pixels present in the two registers will be stored in specific location of stego memory which starts from location number 8193 in SRAM pointed out by stego location identifier.Thus one state machine cycle results in embedding 3 bits each in two pixels of the cover image. After this state machine cycle which takes five clock cycles gets over, the embedding process goes back to first state again to embed the data in all the pixels/number of pixels according to the size of secret message |
| Fig. 4: | Secret Embedding time in 128x128 grayscale images in various approaches |
Timing analysis:
| • | FPGA Master clock frequency = 50 MHZ |
| • | Stego process clock frequency = 100 MHZ (with PLL) |
| • | Clock cycles required to embed secret bits in 1 SRAM location (2 cover pixels;6 message bits) =5 cycles of 100 MHZ |
| • | Size of the image = 128x128 cover |
| • | No of locations in SRAM = 8192 |
| • | Total number of clock cycles for hiding entire information = 8192x5 = 40960 clock cycles |
| • | Total time required = 8192x5x(1/100MHz) = 409.6 microseconds |
The time taken for embedding secret message (two bits/pixel) in a 128x128 grayscale image stored in External SRAM proposed in Rajagopalan et al. (2012b) is 983.04 micro seconds. As the time taken for embedding is not a function of the value of K (i.e.,) number of bits to be embedded in a pixel, same amount of time would have been consumed for 0<K<5. Our proposed method of hardware steganography on Cyclone II FPGA consumes 409.6 microseconds to hide information on the whole pixels of 128x128 grayscale image residing at SRAM, which is 573.44 microseconds less than earlier profound approach in Rajagopalan et al. (2012a). Also this approach surpassed the LFSR based information hiding approach (Sundararaman and Upadhyay, 2011) which resulted in 0.491 milliseconds (Approximately 80.4 microseconds less in proposed approach). The comparison is shown in the graph in Fig. 4.
RESULTS
Synthesis report:
| • | FPGA used: EP2C20F484C7 |
| • | Logic elements utilized: 108 out of 18,752 (< 1%) |
| • | Logic registers used: 82 out of 18,752 (< 1%) |
| • | Pins utilized: 41 out of 315 (3%) |
| • | PLLs used: 1 out of 4 (25%) |
| • | SRAM memory locations used: 16384 Locations (8192 for cover Image and 8192 for stego image) |
Error metrics:
| • | The error metrics i.e. the performance parameters to judge the quality of the Stego image are |
| • | MSE(mean square error) calculated by the equation: |
| • | PSNR(peak signal to noise ratio) calculated by the Equation: |
The quality of the image and the PSNR values are directly proportional. Higher the value, improved quality can be obtained. The MSE and PSNR values obtained for the four different images using the LABVIEW code is tabulated in Table 2 for better understanding of the quality improvement in the proposed methodology.
Sample cover and Stego images:
| • | The cover images and the stego images are shown in Fig. 5 and 6. It is observed that the imperceptibility is enhanced as compared to the other methods. In addition to this, the robustness is improved due to extraction procedure which is not the simple LSB substitution |
| Table 2: | Error metrics result |
| *USC: University of Southern California (Test Image) | |
| Fig. 5(a-d): | Cover image (a) Gandhiji, (b) Pepper, (c) USC 5.2.10 and (d) USC House |
| Fig. 6(a-d): | Stego image (a) Gandhiji, (b) Pepper, (c) USC 5.2.10 and (d) USC House |
CONCLUSION
A spatial domain hardware steganographic system on gray scale images has been proposed in this paper. Earlier works proposed in hardware architecture for stego systems on FPGA concentrated on traversal path, randomness with LFSR, shuffler etc.,. One of this work’s main objectives are deciding the secret message to be embedded based on the secret bits itself using 4-bit convolution encoder (3,1). Also the proposed work parallely hides the secret bits in the two pixels stored in a SRAM location by accessing the two cover pixels in one clock cycle and storing back the stego pixels after modification and this concurrent hiding resulted in minimizing the total time taken to embed the secret information in entire cover image compared to the previous works which used techniques that operated on only one pixel per clock cycle. As varying the arrangement of XOR gates in convolution encoder and usage of LSBs of n-bit convolution encoder for the encoding purpose can find a place in camouflage, future work can be focussed on this direction. Also FPGA based image steganographic systems using various image processing operations needs attention.
ACKNOWLEDGMENT
The authors wish to express their sincere thanks to DRDO, New Delhi for their financial support (ERIP/ER/1003836/M/01/1230). They also wish to acknowledge SASTRA University, Thanjavur for extending infrastructural support to carry out the study.