Abstract: This study presents near-threshold computing and performance optimization for MCML circuits to attain both low power dissipation and high speed. Unlike the traditional MCML circuits, the output swing of the MCML circuits used in this paper is larger than the threshold voltage of NMOS transistors and the NMOS logic blocks of the MCML circuits operate on linear region, so that their source voltages can be effectively reduced. A near-threshold decimal counter is optimized in term of power dissipation and delay by using the proposed optimization algorithms. All circuits are simulated using SMIC 130 nm technology by varying supply voltage from 1.3 V to 0.4 V with 0.1 V step. The results show that the power consumption of the optimized MCML circuits can effetely be reduced by lowering the supply voltage over a wide range of frequencies.
INTRODUCTION
In MOS Current-Mode Logic (MCML) circuit, source voltage VDD represents logic 1, while VDD-ΔV (ΔV represents output voltage swing) means logic 0. Obviously, its swing is much little than conventional CMOS circuits and thus the circuits designed with the MCML techniques can operate over a higher speed (Yamashina and Yamada, 1992; Alioto and Palumbo, 2003). Therefore, MCML is widely used for high-speed applications such as high-speed processors and Gbps multiplexers for optical transceivers (Tanabe et al., 2001; Musicer and Rabaey, 2000). Another interesting advantage of this technique is that their speed and power consumption can be simply adjusted by altering the bias current of the gates without the need for resizing the devices (Anis and Elmasry, 2002; Hi and Li, 2013).
However, the power consumption of a MCML circuit with given voltage and current is a constant. Therefore, the power consumption of the MCML circuit is independent of frequency (Hi and Li, 2013). This means that the MCML circuits have large static power due to their constant operation currents, especially for low-frequency operations (Anis and Elmasry, 2002). Nowadays, energy has become one of the most valuable sources. With the increasing demand for battery-operated mobile platforms like portable computers, laptops, cellular phones, wireless sensors and biomedical applications that require ultra-low energy dissipations, energy-efficient designs have become more and more important for nanometer CMOS circuits (Zhang et al., 2011).
In nanometer CMOS digital circuits, power dissipation consists mostly of dynamic and static components. One direct solution for reducing energy consumption of conventional CMOS circuits is to scale supply voltage. In the conventional CMOS circuits, scaling supply voltage to sub-threshold region can reach minimum energy consumption (Markovic et al., 2010). However, sub-threshold circuits only fit low-performance (50 kHz-5 MHZ) application (Markovic et al., 2010). For conventional CMOS circuits, scaling supply voltage to medium-voltage region can not only keep reasonable speed but also reduce energy consumption (Hu and Chen, 2012).
Similarly, the power consumption of the MCML circuits can also be reduced by lowering the supply voltage (Wu and Hu, 2011). To the best of our knowledge, the performance optimization on near-threshold MCML circuits has not been presented. In order to attain both low power dissipation and high speed, near-threshold computing for MCML circuits is addressed in this work. The performance optimization for near-threshold MCML circuits is also proposed.
MCML CIRCUITS
The basic MCML inverter/buffer and its bias circuit are shown in Fig. 1 (Yamashina and Yamada, 1992; Hassan et al., 2005). The MCML inverter is composed of three main parts: the load transistors P1 and P2, the full differential pull down switch network consisting of N1 and N2 and the current source transistor Ns.
| Fig. 1: | MCML inverter/buffer and its bias circuit |
The load transistors are designed to operate at linear region with the help of the control voltage Vrfp produced by the bias circuit, which also controls the output logic swings. The Pull-down Network (PDN) NMOS N1 and N2 are used to perform logic operation. The NMOS Ns is used to provide the constant current source, which is mirrored from the current source in the bias circuit. In the MCML, the two signals Vrfp and Vrfn are generated from the bias circuit to ensure the proper operating for output voltage swings and to provide the constant bias current. This construction decide that VOH = VDD and VOL = VDD-IBRD, where RD is the PMOS load resistance. The logic swing:
ΔV = VOH - VOL = IBRD.
The traditional MCML circuits make the pull-down network operate in saturated region. To achieve this goal, the output swing must be controlled below threshold voltage. With the scaling-down of technology dimension, the threshold voltage of transistors is reduced. The typical threshold voltage of transistors is between 0.2 and 0.3 when dimension is below 130 nm. In order to make the pull-down network operate in saturated region, the output swing must be smaller than this threshold voltage, which may lead to bad performance on noise margin. In order to solve this problem, the pull-down network operates in linear region. In other words, the output swing is larger than threshold voltage. All MCML circuits mentioned in this work are worked with an output swing of 0.3 V.
MCML is a type of differential logic with differential input logic tree. Therefore, the design of the MCML PDN is similar to other differential logic styles such as DCVSL and DSL. The complex logic functions can be realized by replacing N1 and N2 with NMOS logic trees. When we design a MCML circuit, two parts can be divided. One part is Bias Circuit and another part is logic circuit. The MCML basic gate cells such as AND2/NAND2, OR2/NOR2, XOR2/XNOR2 and AND3/NAND3 are shown in Fig. 2.
The power consumption of MCML circuits can be expressed as:
| (1) |
where, I is source current. Easily, energy consumption per cycle can be expressed as:
| (2) |
where, T is operation period and f is frequency. In Eq. 2, a direct solution for reducing energy consumption is to scale down supply voltage, since the total energy is reduced linearly as supply voltage scales down. Scaling supply voltage to near-threshold region is an attractive approach.
ANALYSIS MODELING OF MCML CIRCUITS
The design variables in MCML circuits include mostly the circuit bias current (I), PMOS load transistors sizes (Wp and Lp), transistors sizes of the NMOS differential pull-down network (Wn, Ln), transistors sizes of current source (Ws, Ls) and the current source bias voltage (Vrfn).
The performance parameters in MCML circuits include mostly circuit delay td, total power dissipation P, voltage swing ΔV, voltage gain Av, noise margin NM, voltage swing ratio VSR and the signal slope ratio SSR. In order to carry out performance optimization for near-threshold MCML circuits, the relations between performance parameters and design variables should be established (Musa and Shams, 2010).
Delay: The PMOS transistors are worked as ideal resistances with a value of R. The total capacitance can be departed into two parts, the internal one and the external one. Internal one consists of Cgd and Cdb, they are the gate-drain overlap and drain diffusion capacitances of the MOS, respectively. The external load capacitance is CL that consists of the sum of wiring and total fan-out capacitances of circuits. Using first-order circuit analysis, circuit delay td is approximated by:
| (3) |
where, C is expressed as:
| (4) |
DC voltage gain: The DC voltage gain Av is a key parameter for the regeneration and stability in a MCML circuit.
| Fig. 2: | Basic gate cells based on MCML |
It should not be smaller than 1.4. Av can be expressed as:
| (5) |
where, μn is the electron mobility, Cox is the oxide capacitance of the MOS transistor, Vy and Vx are the voltages between internal nodes.
Noise margin: It is significant to achieve a sufficiently large noise margin in MCML circuits because of its reduced voltage swing. But with a unique frame, MCML circuits can accept a small value for NM (Noise Margin). Theoretically, the maximum NM is ΔV, as Av is large enough. Practically, 0.4 ΔV is sufficient to ensure proper circuit operation.
Voltage swing ratio: In reality, not all the current I generated by the NMOS transistor Ms is steered to the ON branch, a part of the current I flows to the OFF branch and thus the output voltage swing reduces. This issue is more severe in cascaded circuits because the quality of current switching will continue to drop. To solve this problem, the current flowing through the OFF branch must be constrained to a limited percent of total current. VSR (Voltage Swing Ratio) is defined as the ratio between the current in the ON branch Ion and the total current. It can be expressed as:
| (6) |
where, VSRu and VSRl are the values of VSR at the upper and lower levels of the MCML circuit, respectively. In order to achieve a VSR of 95%, VSRu and VSRl should not be smaller than 97%.
Signal slope ratio: Speed is an important issue in MCML circuits. A metric is needed to ensure that their output response will not have long rise/fall time trf with respect to td. SSR (Signal Slope Ratio) is defined as the ratio between trf and td and it is expressed as:
| (7) |
To get a reasonable output waveform, SSR is limited to a maximum of 5.
Device size of differential pair transistors: A large width of differential pair transistors increases Av and at the same time adds up to the load capacitance. Hence, in order to get a reasonable channel width, a compromise between CL and Av must be made.
As is known to all, an increasing channel length adds up to the parasitic capacitance and thus results in a longer time delay. Therefore, for differential pair transistors, the channel length should be chosen as minimum size of the technology.
Current source design variable: The current source transistor Ms has two main influence factors. One is the current source common-mode rejection ratio (CMRR) and another is the value I of the current source. Increasing the length of the transistor Ms can add up to the output resistance Rout of the bias current source, which will lead to an advance on CMRR. The minimum Rout is determined by setting the CMRR of the circuit to a value above 20.
The bias voltage Vrfn controls the amount of current supplied to the circuit.
Optimization of MCML circuits: As mentioned in section 3, the design of MCML circuits is a complex and challenging task. Every variable or parameter can influence the performance of the whole circuit. In order to get proper operation and a good performance of the MCML circuits, the limits that should be satisfied are listed in 8-19 according to the above discussions:
| (8) |
| (9) |
| (10) |
| (11) |
| (12) |
| (13) |
| (14) |
| (15) |
| (16) |
| (17) |
| (18) |
| (19) |
Based on the conditions listed in (8-19), the optimization procedure for near-threshold MCML circuits is illustrated in Fig. 3. In optimization procedure, the channel width of MOS transistors varies from 2xWmin to 2 um with 65 nm step, while the channel length of MOS transistors varies from 2xLmin to 0.65 μm by 65 nm step.
Simulations of MCML circuits: In this work, the performance and energy consumption of the static CMOS logic decimal counter is acted as a criterion. As it mentioned carlier, if the pull-down network of MCML operate in saturated region, it may result in bad performance with the scaling-down of technology dimension. We explored that whether the pull-down network can work in linear region or not. With the simulation of some basic MCML gates, the outcome is certain. All the MCML circuits mentioned below are worked with an output swing of 0.3 V.
Power dissipation of MCML circuits with a standard source voltage: In order to investigate the performance of the MCML circuits in near-threshold region, the simulation of different MCML cells in various frequencies with standard source voltage is needed. HSPICE simulations for AND2/NAND2, OR2/NOR2, XOR2/XNOR2 and decimal counter have been carried out with SMIC 130 nm technology as is shown in Fig. 4.
Form Fig. 4, the power consumptions of MCML circuits is nearly independent of frequency. It verifies that MCML circuits have a great advantage in high-speed applications. Power consumptions of the decimal counter based on MCML are compared with the decimal counter based on conventional static CMOS in Fig. 5 for various frequencies with 1.3 V standard source voltage.
Near-threshold computing of MCML circuits: In order to attain both low power dissipation and high speed, near-threshold computing for MCML circuits is addressed in this section.
The near-threshold decimal counter has been optimized in term of power dissipation and delay by using the proposed performance optimization algorithms. The circuits are simulated by varying supply voltage from 1.3 V to 0.4 V with 0.1 V step. The power dissipations of the near-threshold decimal counter using the performance optimization algorithm are shown in Fig. 6 with various supply voltages at 500 MHZ.
| Fig. 3: | Optimization procedure for near-threshold MCML circuits |
| Fig. 4: | Power consumptions of the AND2/NAND2, OR2/NOR2, XOR2/XNOR2 and decimal counter based on MCML in various frequencies with standard source voltage |
Scaling down the supply voltage can save energy consumptions effectively. The power consumption of the counter at 0.4 and 0.7V supply voltage is only 11.16 and 50.1% of 1.3V supply voltage, respectively.
| Fig. 5: | Power consumption comparisons of the decimal counters based on MCML and conventional static CMOS in various frequencies with 1.3V standard source voltage |
| Fig. 6: | Power consumptions of the decimal counter based on MCML in near-threshold regions |
In order to give a visual contrast between standard MCML and near-threshold MCML decimal counters, their power consumptions with different source voltages in various frequencies are given in Fig. 7. In Fig. 7, the decimal counter based on MCML operates from 0.4 V to 1.3 V source voltage and the working frequency is from 100 MHz to 1.4 GHz.
From Fig. 7, Power consumption reduces dramatically as the source voltage decreases, while the change of frequencies nearly have no influence in power dissipations.
| Fig. 7: | Power consumptions of the MCML decimal counter with different source voltages in various frequencies |
CONCLUSION
MOS Current-Mode Logic (MCML) is usually used for high-speed applications. However, the MCML circuits have large static power because of their constant operation currents. The power consumption of the MCML circuits can also be reduced by lowering the supply voltage. To the best of our knowledge, the performance optimization on near-threshold MCML circuits has not been presented. In order to attain both low power dissipation and high speed, near-threshold computing for MCML circuits has been addressed in this work. The performance optimization for near-threshold MCML circuits is also proposed.
A near-threshold decimal counter has been optimized in term of power dissipation and delay by using the proposed performance optimization algorithms. The results show that the power consumption of the optimized MCML circuits can effetely be reduced by lowering the supply voltage over a wide range of frequencies.
ACKNOWLEDGMENTS
This study was supported by the Key Program of National Natural Science of China (No. 61131001), National Natural Science Foundation of China (No. 61271137 and No. 61071049), Ningbo Natural Science Foundation (2011A610102) and sponsored by K.C. Wong Magna Fund in Ningbo University.