Abstract: In order to reduce IP (Intellectual Property) infringements in VLSI (Very Large Scale Integration), many IP protection methods have been proposed. These methods have involved knowledge in fields of microelectronics, information hiding and embedded system. As a new field, IP protection can greatly reduce ownership misappropriation but it is faced with numerous challenges. On the basis of existing fundamental theories and engineering technologies, IP protection has rapidly developed in recent years. This study introduced IP protection in terms of concepts, characteristics and architecture. The challenges of IP protection technologies were analyzed. This study focused on the latest research improvement of IP protection technologies. The difficulties of digital watermarks on overhead, security, amounts were stated concretely. Meanwhile, this study presented some research methods for reference, such as multiple IP watermarking technology, models for watermark embedding and optimal computation, IP blind forensics technology and methods for evaluating watermark performance.
INTRODUCTION
In the development of integrated circuit industry, low power and high integration are still the focus of technological competition (Girard, 2002; McCluskey et al., 2003). With the improvement of integration, the Moore’s law still meets the demands of integration technology as before. However, in SoC (System on Chip), the contradiction between design ability and technological level has become a prominent obstacle of SoC development. If it starts all over again, it will not doubt increase difficulties and complexity and even the time to go public cannot be guaranteed. In this case, an IP reuse technology has been presented for solving this problem. The technology is to use predesigned, implemented and verified integrated circuit modules in SoC design, which has greatly reduced design level, complexity and design cycle. Recently, IP reuse technology has become a mainstream in Very Large Scale Integration (VLSI) (Abdel-Hamid et al., 2005). Meanwhile, application of the technology can bring the risk of misappropriation, which will damage the interests of IP designers seriously.
The statistics of Intel cooperation show that misappropriation of integrated circuit IP core could reduce the cost of development more than 80% and shorten the development time by one and a half years. The loss to industry caused by IP misappropriation has reached to five billion dollars. The disputes over intellectual property have brought not only huge financial loss but also damage to international reputation of enterprise brand and cooperation with customers. Confronting with masses of IP copyright disputes, the protection of reused IP core has been widely concerned all over the world.
To facilitate the development of VLSI, it is essential to reduce copyright disputes and misappropriation. In this case, the study on IP protection technologies has significant impact on sound development of national integrated circuit.
DEFINITIONS AND CHARACTERISTICS OF IP WATERMARKING TECHNOLOGY
IP watermarking technology is developed as a novel technology by inserting secret information into IP circuits for ownership identification. The concept was derived from the safety standard cell library provided by Foundry. At present, IP watermarking technology is primarily to hide specific information into reused modules of integrated circuit.
| Fig. 1: | Architecture of digital IP watermarking technology |
The research results of IP watermarking technology can be applied in army, department of state secrets or company with core technology. As is shown in Fig. 1, IP watermarking technology is divided into four design levels. From high to low, they are systematic level, behavioral level, architectural level and physical level (Kahng et al., 2001; Lach et al., 1998). Accordingly, VSIA alliance classifies reused IP cores into three classes, respectively soft IP, firm IP and hard IP.
IP watermarking is different from multimedia watermarking since the user data cannot be altered. The features of IP watermarking are stated as follows:
| • | Transparency: It is a complicated task to design and verify IP cores. Since IP cores require strictly on correct functionality and precise timing, the watermark embedding of IP cores has no impact on functionality. Meanwhile, the invisibility of watermarks is necessary |
| • | Security: The watermarks should be embedded into IP design in secret, protecting it from being found and removed by illegal users. In this case, resistance to attacks should be taken into account in design of IP watermarking algorithm |
| • | Reliability: It is an important indicator for evaluating IP watermarking algorithm. Two aspects are included. One is robustness, which measures resistance of watermarks against illegal attacks and the number of undetected watermarks in IP design. The other one is false positive, which represents the probability of watermarks being found in a non-watermarked design |
| • | Watermark capacity: The IP watermarking algorithm should insert enough ownership information for identifying copyright of IP design. The information will be extracted and considered as evidence in court. However, the size of embedded information should be small enough in order to reduce performance overhead. In this case, the watermark capacity is a contradiction, which needs a systematic consideration |
| • | Performance overhead: The watermarking of IP design is one of the IP protection means, which will affect performance of IP design to some extent. Consequently, it is necessary to evaluate performances in terms of area (resource), timing, etc |
CHALLENGES OF IP WATERMARKING TECHNOLOGY
At present, IP reuse technology has no universal and effective protection standard. The manufacturers of IP cores expect no misappropriation and illegal alteration on their products and less time and energy in maintenance and verification of IP cores as well. On the other hand, the customers hope IP cores they bought are creditable, which will improve the efficiency of SOC design and reduce design risks.
| Table 1: | Performance comparison for several IP watermarking schemes |
The VSIA alliance brings great convenience for IP manufacturers and SOC designers in IP protection and searching. However, IP design standards of these companies are various, which may cause the problems of long verification cycle, high failure rate and high cost. In this case, the research on reused IP protection technology cannot meet the demands for real-time protection and ownership verification in availability. Table 1 shows that present IP watermarking technologies are still confronted with three challenges:
| • | Low security: In majority of existing IP watermarking methods, watermark embedding always leaves trace of circuit alteration. The trace will be easily detected and found by users and related EDA tools. After suffering various conventional processing and hostile attacks, the embedded watermarks will be damaged or removed. In this case, the complete watermarks will be hard to extract for verification |
| • | Small watermark capacity: As is known in Table 1, the majority of watermark embedding schemes will use large redundant structure for watermark embedding in order to exert no impact on performance. With restriction of watermark structure in existing IP watermarking methods, it is hard to improve watermark capacity in specific IP redundant structure |
| • | High performance overhead: As is shown in Table 1, most of IP watermark will produce numerous additional constraints at various abstract design levels. These additional constraints always lead to extra hardware overhead. In this case, the overhead in terms of embedding time, circuit area, speed and power will accordingly increase |
RESEARCH STATUS AND ANALYSIS
Research progress of FPGA-based IP watermarking technology: FPGA-based IP watermarking technology at physical design level:
In recent years, IP watermarking technologies at physical design level have been widely researched. In University of Verginia, Lach et al. (1998) firstly presented FPGA-based IP watermarking method. Watermarks were mapped into additional constraints by using constraints generator and then inserted into the physical layout with the satisfiability in NP problem solving. In the constraints-based watermarking scheme proposed by Qu (2002), the watermark is divided into two parts: public and private. The public watermark can be detected in public and the third party is responsible for IP identification, while private watermark can only be detected by several authorized users to solve the difficulties in IP detection and authorization. Since, watermark embedding in back-end process of physical design level is more secured, a watermarking scheme based on back-end process of physical design level was proposed by Lach et al. (2001) in Kochi University. The scheme abstracted physical layout as figure by using graph theory and topology. Watermarks were embedded into design with searching algorithm and optimizing algorithm (Nie et al., 2005). For better flexibility of watermarking scheme based on physical layout, Halder et al. (2009) in University of Calcutta took graph corresponding to digital system design as input and embedded watermarks into encrypted graph by using LFSR-based locking scheme. However, this watermarking scheme imposed many restrictions on watermark embedding, making watermark detection much difficult (Halder et al., 2009). In Indian statistical institute (Saha and Sur-Kolay, 2010) proposed a novel secure IP watermarking scheme at physical design level. VLSI design at physical design level could be protected directly and indirectly since the use of encryption algorithm and watermarking algorithm. The scheme has decreased difficulty of watermark detection and overhead caused by watermark embedding. Since FPGA platform has good performance on data processing and algorithm verification, FPGA-based IP watermarking algorithm at physical design level was proposed by Marolia (2008) in Georgia Institute of Technology. The watermarks were inserted by altering wires in FPGA-based design. Lu and Wang (2004) proposed timing constraints based FPGA watermarking scheme in front-end process. The watermarks were embedded into timing constrains of non-critical paths without affecting performance. After that, the bitfile of watermarked design was generated. Since security of watermarking algorithms based on designs at physical design level is much lower (Miao et al., 2007) inserted ownership information into unique architecture of FPGA for protecting IP cores. Nie et al. (2010) designed a verification platform of IP watermarks. The design process was introduced concretely and the effect of the proposed platform in IP watermark verification was analyzed as well. Liang et al. (2011a) proposed a chaotic mapping based IP watermarking algorithm at physical design level. The algorithm has low impact on performance in terms of circuit area, speed, etc.
FPGA-based IP watermarking technology at architectural design level: In this field (Ziener et al., 2010; Schmid et al., 2008) in the University of Erlangen-Nuremberg firstly introduced a new scheme for watermarking of IP cores for FPGA architectures. The watermark was detected at the power supply pins of FPGA. Moreover, the author’s team presented an IP watermarking technology on the basis of netlist structure. The scheme restricted dynamically addressable part of the logic table in order to free spaces for watermark insertion. These two schemes will produce many extra traces of circuit alteration, causing a severe decline of watermark security. In the Southern Illinois University (Khan and Tragoudas, 2005) proposed a watermark embedding method in back-end process. The watermarks were embedded by altering netlist structure with redundancy addition and removal technology. Once a redundant connection was added to circuit, a series of new redundant connections may be generated. The function of new circuit will be the same with original circuit after removing these redundant connections. If the new circuit meets indicator of timing and some other indicators, the original circuit can be replaced with the new circuit. It is called redundancy addition and removing technology. In the scheme proposed by Kirovski et al. (2006), the watermarks were mapped into a set of additional constraints and then submitted to synthesis tool. The synthesis tool controlled logic synthesis, optimization and technology mapping of structure design level and finally generated unique output watermark vectors. The scheme requested strictly on the length of constraints. Shorter length of constraints will bring threat to security. On contrary, overlong length of constraints will cause larger hardware overhead. Xu et al. (2011) proposed an IP watermarking method by adding redundant logics into design. The ownership information was compressed and encrypted. With specific linear combination expression, the information was transformed into watermark bits and watermark positions. The watermark bits were finally inserted into FPGA based design dispersedly with method shown in Fig. 2. In this scheme, the performance in terms of watermark capacity, resource overhead and security was encouraging.
FPGA-based IP watermarking technology at behavioral design level: In research results of FPGA IP watermarking schemes at behavioral design level (Castillo et al., 2006) made use of the special internal architecture of FPGA and inserted watermarks into interspaces in used LUTs (Table 1) and unused LUTs.
| Fig. 2: | Example for watermark embedding |
The hardware overhead is mainly caused by the circuit logic for extracting watermarks. The logic will write watermarks to output port after detecting specific input sequence. By comparing with scheme proposed (Raj et al., 2011), watermark extraction is more convenient. However, the circuit for watermark extraction is vulnerable as well. Yu and Zhu (2011) proposed a watermarking method for protecting soft IP cores. The data of image and text are embedded into soft IP design in forms of specific bit stream. The on-site detection is implemented with low overhead. In method presented by Cai et al. (2007), the watermark constraints were dispersedly inserted into a set of watermark positions which were randomly selected in physical layout. Moreover, the author’s team implemented a constraints-based watermarking system for protecting soft IP cores and hard IP cores. Their schemes are applicable for VLSI design and full-custom designs, which were superior to traditional constraints-based watermarking schemes. Sun et al. (2006) introduced an IP watermarking method by using buffer insertion technique. In addition, a hierarchical IP watermarking technology at behavioral design level on basis of constraints-based watermarking methods. Lin et al. (2007) proposed a HDL-based IP module protection method by inserting module of watermark detection into HDL code. The method has better ability against forgery attacks.
FPGA-based IP watermarking technology at systematic design level: Research results of IP watermarking technologies are rarely reported at systematic design level. (Chapman and Durrani, 2000) in the Strathclyde University proposed an IP protection for DSP algorithm implemented on SOC. The watermark was generated and embedded into partitions of high level filter design. The illegal users cannot obtain the watermark easily. However, the security is lower due to the short length of watermarks.
| Fig. 3: | Example for embedding watermarks into FSM-based IP core |
Research progress of FSM-based IP watermarking technology: IP watermarking technologies based on FSM (Finite State Machine) have been widely researched in field of digital watermark. As is shown in Fig. 3 Torunoglu and Charbon (2000) added some unused transitions into original STG (State Transition Graph) and constructed an Euler path with the newly added transitions for indicating watermark. Oliveira (2001) divided 128bit watermarks into a set of watermark fragments according to the bit wide of input signal. These fragments, taken as an input sequence, were embedded by altering state of STG. For strengthening performance of watermark detection. Abdel-Hamid and Tahar (2008) proposed to insert watermarks into sequential circuit on basis of FSM in succession. This kind of watermarking algorithm shows certain randomness under control of key K. In this case, different schemes to add transitions will be generated if different designers input different keys. In watermark detection, given specific initial state and watermark input sequence, it is easily to read output sequence of watermarks.
In order to improve security of FSM based IP watermarking methods at behavioral design level Xu and Zhu (2011) proposed a FSM based watermarking scheme for soft IP protection. It is an improvement of original FSM-based IP watermarking technology, with some problems like low security and high power overhead still remaining. Cui et al. (2008) proposed to embed watermarks into architecture of single scan chain with FSM reduction technique. The traceability is guaranteed since FSM reduction technique does no damage to watermarks. The watermarks will be detected at lower design levels even in a packaged chip. In FSM base watermarking schemes, the team proposed a simple-designed IP protection scheme, which embedded watermarks by reordering scan cells between scan chains but its security and overhead remains to be improved. Liang et al. (2011b) introduced an FSM based IP watermarking algorithm with better performance on security and hardware overhead.
Research progress of testable IP watermarking technology: In recent years, testable IP watermarking technology has been a research hotspot at home and abroad, which concentrate on scan chains based IP watermarking. For instance Fan (2008) added watermark generation circuit in reusable IP design and proposed five feasible watermark hiding methods. According to embedding rules, watermark can be detected at output pin of the chip on site. However, once make the embedding rule public, the watermark generation circuit is easy to remove. In watermarking schemes based on scan chains and scan forest, the method by Saha and Sur-Kolay (2010) proposed to protect IP by altering both the scan tree and single scan chain, separately embedding signatures of the owner of physical design tool and that of the logic design tool, in which watermark detection was difficult. In methods proposed by Cui and Chang (2009), Chang and Cui (2010) and Cui et al. (2011) watermark was inserted by reordering the scan cells in scan chains, which is described in Fig. 4. Additional constraints generated by the owner's digital signature have been imposed on the NP-hard problem of ordering the scan cells to achieve a watermarked solution which minimizes the penalty on power and cost of testing. The ownership legitimacy can be publicly authenticated on-site by IP buyers after the chip has been packaged. Liang et al. (2011a) proposed an IP protection method by watermarking minimum correlation of vectors based multiple scan chains. It provides an effective approach for improving fraction of coverage. However, the ability against collusion attacks and performance on hardware overhead still exist room for improvement.
Research progress of other IP protection technologies: “Tag” technology: To identify authenticity of chip by inserting an electronic “tag” into chip with good reliability and traceability. An EPIC (Ending Piracy of Integrated Circuit) technology was proposed by Roy et al. (2008) for supervising chip manufacture. The key is embedded into circuit in advance. The chip cannot enter into market through routine test without activation. Furthermore, a bus based “lock and unlock” scheme was proposed for hardware IP protection. Its implementation requires certain hardware overhead (circuit, pins, etc.) but with good concealment and security. Even so, the scheme can still only supervise chip manufacture and test but not involve traceability of IP watermarks after chip is sold.
| Fig. 4(a-d): | Example for embedding watermarks into testable IP core |
| Fig. 5: | BPUF Cell Displayed by FPGA Editor |
A tag technology for protecting ASIC (Application Specific Integrated Circuit) IP core was proposed by (Goren et al, 2010). A “secure tag”, with ownership information stored, is placed in IP core. Meanwhile, an “external receiver” is set for detecting the existence of the tag. The independency of “tag” can deter misappropriation to some extent but the “tag” may be easy to be removed or damaged. Methods in Kumar et al. (2008), Guajardo et al. (2007) and Kumar et al. (2008) used the unique physical feature and variability of single silicon slice in IC manufacture and generated RFID (Radio Frequency Identification Devices) “tag”. After that, the “tag” is integrated into chip for preventing chip clone. As shown in Fig. 5, security has been greatly improved but high design cost and RFID work environment restrict the development of this technology.
Fingerprint technology. Various users can obtain different versions of IP cores with identification. The use of this technology can identify responsibility in property dispute due to the uniqueness of fingerprint. The difficulty lies in generation of many different IP cores with the same function and technology indicators in design process. Lach et al. (2001) proposed an IP fingerprint technology based on partition of problem solving. An initial problem solving is divided into many parts, each one of which is realized with different forms. The IP module with user fingerprint is generated by selecting and combining forms of different parts. However, this technology can only be implemented on certain VLSI design level. Furthermore, high design cost and low ability against collusion attacks make its application be limited.
OUTSTANDING ISSUES IN IP WATERMARKING TECHNOLOGY
To make reusable IP watermarking technology be safely applied in practice, it is necessary to design a more effective IP watermarking method. However, the research on this aspect remains in primary stage. To develop into mature application technology need further innovative research. Consequently, there are several problems in digital IP watermarking technology to be solved, which will provide guidance for future watermarking technology.
Multiple IP watermarking technology: In research fields of digital IP watermarking, multiple IP watermarking can always perform several application functions, which is impossible for traditional watermarking technology to replicate. Multiple IP watermarking has great improvement in applied range and extensibility, making it applicable in more complicated environment. Nevertheless, it gives transparency of system away since more watermarks will be embedded into design than that in single watermarking scheme. The more design levels are watermarked, the larger hardware overhead it takes. At present, multiple IP watermarking technology still stays on simple superimposition of several watermarks. Although with strengths in watermark number and robustness, multiple IP watermarking technology will bring certain complexity as well. Consequently, research on this aspect will provide approaches for the development of IP watermarking in integrated circuit, such as watermark capacity, security, etc.
IP watermark embedding models and optimization models: To build models of IP watermark embedding and optimization is a critical part of IP watermarking technology. Correlation and compatibility between IP watermark vectors are related to watermark structure in watermarked circuit and watermark structure depends on size of redundant information in circuit carrier. Consequently, real application of IP watermarking scheme will consider logic synthesis and optimization of circuit in various abstract design levels. In original circuit, states of redundant information and ordering of signal names may be altered, which will lead to larger structure of some redundant information and lower security of watermarks. Study on methods of watermark embedding and optimization, construction of watermark architecture, optimal condition of watermark embedding based on good security and reliability will be development trend of IP watermarking technology.
Watermark detection: In general, user information or identification of IP core will be used for generation of unique fingerprint with specific encryption algorithm. The fingerprint information is then inserted into IP attribute document secretly, which will be distributed to various users. Once a user is suspected to reuse IP design illegally, the fingerprint information will be extracted for ownership authentication. If succeed, the illegal IP user will be found by decrypting the extracted information. Since this method requires participation of the third party, it will bring many difficulties for IP forensics. To study on blind forensics technology will be crucial in IP forensics.
Watermark evaluation: Performance evaluation is an important part in IP watermarking technology. In order to fully evaluate strengths of IP watermarking and compensate for drawbacks of other watermarking methods, evaluation method of watermark performance will be researched at various abstract levels. Furthermore, corresponding standards will be established as well. At present, performance evaluation of IP watermark mainly consists of security and robustness, which is contradictory mutually. The capacity and strength of embedded watermarks have impact to security and robustness inordinately. For this reason, the compromise scheme among watermark capacity, robustness and security should be overall considered.
CONCLUSION
This study summarized the background, concept and features of IP watermarking technology and analyzed problems in current IP watermarking. Moreover, many challenges and latest progress of IP watermarking are discussed. On the basis of existing theories and research results, some critical research problems, like multiple IP watermarking, model design of watermark embedding optimization, IP detection and performance evaluation, etc., are presented for practical application. These introductions are expected to provide references for researchers in the field of VLSI based IP protection.
ACKNOWLEDGMENTS
This study is partially supported by National Basic Research Program of China (973 Program) under Grant No. 2012CB315801 (2012.1-2015.12, Hunan University). National Natural Science Foundation of China under Grant No.61202462 (2013.1-2015.12, Hunan University of Science and Technology) and No. 61173167,61173169 (2012.1-2015.12, Hunan University), National Natural Science Foundation of Hunan Province and Xiangtan united Foundation under Grant No. 11JJ9014 (2011.1-2013.12, Hunan University of Science and Technology), the planned science and Technology Project of Hunan Province, China under Grant No. 2011 Gk 3156 (2011.6-2013.6, Hunan University of Science and Technology), National Natural Science Foundation of Hunan Province Foundation under Grant No. 13JJ3091 (2014.1-2016.12, Hunan University of Science and Technology).