Abstract: The aim of this work is to show the interest in using the deterministic fractal structures in the building of specific condensers compared to traditional plans condensers. Research relates on MOS condensers of which one of the plates is of fractional dimension. In the case of this work, it is about fractal tree of dimension 1.46 and Sierpinski carpet of dimension 1.89. The capacitive behavior of these particular condensers in which one of the plates is of fractional dimension is compared to traditional plane plate condensers. This study made it possible to note that MOS capacitors with fractional dimension have interests other than the value of the capacities they bring back but on the weakness of the dielectric constant. The study presented here is on the one hand, the development of the technological process of realization of the samples. On the other hand, the extraction of the capacities values of the samples previously mentioned above that are compared with those of the control plans capacities.
INTRODUCTION
Fractal structures are characterized by a geometric self-similarity and fractional dimension (Le-Mehaute, 1990). The study of the electrical model of the input impedance of these structures allows on the one hand to highlight a particular behavior (Niklasson, 1993) called constant phase angle or CPA on the argument curve. On the other hand, it reveals on the frequential evolution module curve of the aforesaid impedance (Haba et al., 1998) a fractional slope zone.
The unique characteristics of these structures namely self-similarity and fractional dimension “D” confer specific physical properties to these materials. It will be made in this work, a comparative study between a plane condenser of entire dimension and a plane condenser having one of the plates of, fractional dimension and the insulator, a silicon oxide (SiO2). The deterministic fractal structures are used in several fields such electronics and the automatic for robust stabilization of feedback systems (Oustaloup, 1999; Joaquin et al., 2006; Haba et al., 2008). They are also found in the areas of mathematics and electrical modeling (Radwan et al., 2011; Shamim et al., 2011), in the field of microwave antennas (Parron et al., 2001; Canet and de Haro, 2004) but almost none is used in the manufacture of MOS capacity. One wants starting from the technological process of manufacturing capacitors on silicon (Haba et al., 1997), to carry out specifics MOS capacity with characteristics properties other than those with a capacity of conventional MOS.
This study is dedicated to the study of the behavior of C as function of V, for capacitive MOS structures for which one of the plates has fractional dimension and to compare them with a capacitor of the kind in conventional plane plates. This has been realized by measuring C(V) and the impedance, from which, it was deduced the capacitors values brought back by each structure and they were compared with the values returned by the control plans capacitors.
GEOMETRICAL CHARACTERISTICS OF PATTERNS OF THE STUDIED STRUCTURES
With a view to conducting a good study, research has brought about the structures of the fractal tree (Fig. 1) with a dimension of Df = 1.465 and in those of the Sierpinski carpet (Gouyet, 1992) (Fig. 1) with a dimension of Df = 1.893; both extracted from the following relation:
| (1) |
where, N is the number of parts created at each iteration and r, the ratio of reduction in length.
Sierpinski Carpet realization process: It is a non-ramified fractal structure with a particular “checkerboard” form. Its design principle is as follows: the initiating element is a full square with a side length L. Each side is divided by r = 3 forming 9 elementary squares. The generating element (structure having one iteration level) is obtained by removing the central square, as shown in the following Fig. 2.
To obtain the second level of iteration, one applies to the 8 remaining elementary squares the principle of generation describes above and so on for the following iterations. The number of elementary squares that the structure contains can be known at any iteration and that is possible by analyzing its generation process described as follows in Table 1.
Fractal tree realization process: The fractal tree is a ramified structure with a fractal dimension Df (Gouyet, 1992) of 1,465 (N = 5 and r = 3) in contrast to Sierpinski carpet.
| Fig. 1 (a-b): | Patterns of the studied samples; (a): Sierpinski carpet and (b): Starry fractal tree |
| Table 1: | Geometric characteristics of Sierpinski carpet |
| Table 2: | Geometric characteristics of the fractal tree |
| Fig. 2 (a-c): | Construction process of Sierpinski carpet; (a): Initiator square; (b):Initiator element (The first level of iteration) and (c): Structure with two levels of iteration |
To shift the level of iteration n to the level of iteration n+1, is applied to all segments generated in previous iteration, the generation process described above. The characteristics related to the number and to the length of branches at a given iteration are defined in the following Table 2.
| Fig. 3 (a-c): | Construction process of the fractal tree; (a):Initiator (iteration level 0); (b): Generator (iteration level 1) and (c): Structure with two levels of iteration |
TECHNOLOGICAL PROCESS OF MAKING STRUCTURES CONSIDERED
The different samples studied were made with the technique of buried structures using three mask levels which are: Pattern without contact studs (1st level), pattern with contact studs (2nd level) and contact studs without pattern (3rd level). The contact studs are the interconnection elements with the test circuit. For manufacturing, one begins by making grow on a naked substrate (P type, NA= 1.1015 cm-3) a thick oxide called field oxide. This oxide will protect these different structures against possible deposition of impurities which may appear on the edges of the samples. One can note that these impurities can generate in these places phenomena conduction or leakage (Fig. 4a). This is followed by a photoetching of the fractal patterns in the oxide with the mask first level (Fig. 4a). It follows then grid oxidation followed by a deposit of Nidos (silicon layer doped by nitrogen SixNy) (Scheid et al., 1994; Dehan et al., 1995) and of polysilicon which will be doped by Boron or phosphorus in order to fix its resistivity (Fig. 4a). In fact, it is the layer of Nidos which will act as protective shield by preventing the doping elements (phosphorus or boron) to pass through the layer of polysilicon to go and “pollute” the grid oxide coating, then the substrate. The last step in manufacture consists in metalizing the front and back faces then, in delimiting the contact studs by photoengraving with the 3rd level of mask. The different stages of technological process summarized in Table 3 make it possible to understand the advance followed to obtain our capacitive structures with fractional impedance (Haba et al., 2005) such as fractal tree and Sierpinski carpet.
Figure 4b is the final structure of each sample obtained at the end of the technological process described in Fig. 4a. It represents the result of the transformation of the naked silicon wafer having undergone steps 1 through 18 of the manufacturing process summarized in Table 3. The C(V) measurements were performed, using these samples (Fractal tree, Sierpinski carpet) with that structure.
It should be noted that one of the important phases of the technological process is the Radio Corporation of America cleaning (Kern and Puotinen, 1970) which precedes any phase of oxidation that occurs through the cycle in the diagram of Fig. 5. In effect, from this cleaning will depend the grid oxide quality of the MOS structure carried out. It eliminates a large proportion of charges that could have been trapped at the Si/SiO2 interface.
A description of the different stages of the oxidation cycle used during the manufacture of the samples is summarized in Table 4.
| Fig. 4a: | Different stages of the technological processes in manufacturing |
| Fig. 4b: | Final structure of the samples |
| Table 3: | Description of the stages in manufacturing technology |
| Cleaning process Si/SiO2 interfaces developed by radio corporation of America. LPCVD: Low pressure chemical Vapor Disposition | |
| Table 4: | Grid oxidation cycle of the samples |
| Fig. 5: | Grid oxidation cycle of the samples |
CHARACTERIZATION OF THE SAMPLES BY C (V) MEASUREMENT
The characterization of the samples takes place on a bench of low frequency measurement (LF) consisting of an automatic machine of test under points SET TC550 composed of a command and control power station associated with a type HP 4284A capacitance meter on which impedance Z (F) and capacity measurements will be done according to the voltage (measurement in C (V)).
The major ranges of measurements of this bench are:
| • | Frequency F: From 20 Hz to 1 MHZ |
| • | Voltage V: From -40V to +40V |
| • | Capacitor C: From 10-15 to 10-5 F |
| • | Impedance Z: From 103 ohms to 109 ohms |
The capacitance-voltage measurements were done in low frequency regime (LF = 1 KHz) with a sinusoidal signal of 100 mV of amplitude. In high frequency regime (HF = 1 MHZ), measurements were made with a sinusoidal signal of 50 mV starting from the accumulation mode towards the inversion mode (Sarrabayrouse and Campabadal, 1990). The shape of the characteristic in C (V) of a control capacitor with plane plates (50.10-4 cm2 of surface) that we obtained is shown in Fig. 6. These measurements give access to many electrical parameters of the MOS capacitor such as: oxide thickness Dox, resistance series * Rb + due to the volume of silicon and the back face contact when this one disturbs measurement, Doping semiconductor Ndop, the flat band voltage VFB, surface potential φs according to the tension Vg applied, the distribution density of states surface NSS and the fixed charges QOX in the oxide.
The measurements made out of C (V), not only make it possible to know the voltage range in which one can use the samples without risk of destroying but also allow us to check if the technological process of realization matches with the specifications.
Evaluation of some parameters: Cox, Dox and Ndop: The capacitance of the oxide layer of a MOS capacitor is given in one relation by Prom (1989) based on several important parameters. These are Cmax, Csc, φso, Dox and εo where:
| • | Cmax is the maximum capacity measured in high frequency |
| • | Csc the capacitance of the semiconductor |
| • | φso the maximum surface potential in accumulation mode |
| • | εo the permittivity of empty space and εox, the constant dielectric of the oxide |
| Fig. 6: | Measure C (Vg) of a test capacity at low and high frequency |
The same equation gives us another relationship between Cox and Dox. By knowing one of the parameters, it was possible to evaluate the other one. The doping of the semiconductor is determined from the curve C (V) obtained at high frequency (1 MHZ). The capacity of the space charge of the semiconductor which is defined by Kar and Dahlke (1972) in another relation allows the extraction of the expression of doping Ndop.
Measurements in C (V) of the structures of Sierpinski carpet and fractal tree: The study in this part is to study the curves of measurements in C (V) of the capacitive MOS structures of which one of the plates has fractional dimension and to compare them with conventional capacitors with plane plates. To do this, one will try to see if the relationship below is checked in the case of the structures of fractional order:
| (2) |
With ε0 the permittivity of empty space, εox, the dielectric constant of the insulator and Dox, the oxide thickness. The curves reflecting their electrical behavior are represented on the graphs of Fig. 7 and 8. Electrical measurements were performed from accumulation areas towards depletion areas on the two samples whose geometrical characteristics are mentioned in Table 5.
This table summarizes geometrical dimensions of the structures carried out for the study. S1 is the elementary surface of a segment in the case of the fractal tree and an elementary square in the case of the Sierpinski carpet. Concerning S2, this one represents the total surface of a branch of star comprising 3125 elementary segments. Being given that the complete structure of the fractal tree comprises 6 branches, then S3 represents the total surface of the sample having 5 levels of iterations.
| Table 5: | Geometrical characteristics of the samples |
| Fig. 7: | Curve C (V) of a MOS capacitor of which one of the plates is the fractal tree with 5 levels of iteration |
| Fig. 8: | Curve C (V) of a MOS capacitor of which one of the plates is the Sierpinski carpet with 5 levels of iteration |
| Table 6: | Comparison of oxide thicknesses calculated and measured of two MOS structures with one plate of fractional dimension (accumulation mode) |
With regard to the Sierpinski carpet, S2 represents the total surface of the sample comprising 32768 elementary squares.
Measurements were made at 1 KHz and at 1 MHZ. One cannot on the two curves obtained at 1 KHz that the accumulation mode and the depletion mode are done normally. On the other hand, when the frequency is at 1 MHZ, there is a very important series resistance which hides all the electrical behavior of the various structures. This shows experimentally that, one cannot bring back the surface of these structures to a single surface as it is possible in the case of a capacitor with plane plates (see curve in C (V) measurement of the test condenser).
The C (V) measurements technic at the frequencies of 1 KHz and 1 MHZ on test capacitors present on each substrate in accumulation mode have allowed to know exactly the real thicknesses Dox of oxide present on each substrate. The same measurements also make it possible to extract the value of the capacities CF brought back by each sample. The theoretical calculation of the thickness from the Eq. 2 is summarized in the Table 6.
One can note that from the linear relationship previously defined Eq. 2, one obtains oxide thickness values completely disproportionate compared to those obtained by measurement. The fact of obtaining too high oxide thicknesses and especially at high frequency (1 MHZ), leads us to say that these MOS capacitors cannot be described by a first order linear law (Haba et al., 2007).
Now, let us try to compare at equal surface and always in accumulation mode, two types of condenser such as one has two plane plates and the other has one of its plates of fractional dimension. To do this, one will choose the two structures mentioned above and then, one will calculate on the basis of relation (2), the equivalent plane capacity as summarized in the following Table 7.
| Table 7: | Compare for the same surface of the plates, the equivalent capacitor CPEQ and the capacitor of which one of the plates is of fractional order (FC) |
As in reference to the Eq. 2, this table presents the value of the CPeq capacities which would be given by a plan condenser having same surfaces and the same oxide thickness.
On equal surface, one can note that whatever the work frequency, the value of the capacitor with plane plate is always greater than the capacitor of which one of the plates is of fractional order. In terms of capacity of condenser, CPeq presents the best assets. Regarding the capacity of the capacitor CF, its use is equivalent to a standard capacitor:
| • | Made up with either smaller plates |
| • | Or containing a dielectric whose εr is lower |
| • | Or with a higher oxide thickness |
By using this kind of condenser, one can neither gain in terms of surface, nor in terms of oxide thickness but rather in terms of low dielectric permittivity.
CONCLUSION
One can just see that the deterministic fractal structures obtained by microelectronic process have interests other than the value of the capacities they bring back compared with those of plans condensers. At equal surface, the capacity CF behaves as a plane condenser having dielectric whose εr would be lower. Such a material with low dielectric permittivity would be recommended in the area of absorption or emission of electromagnetic fields. As a matter of fact, the energy received by such a material is transformed into another form that is to say, in heat; which limits the power of the reflected waves.
So, one of the fields of application would be the field of radar and thus, of the stealth which will be the subject of future research.