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FHSS-FSK Modulator Design and Implementation for a Wireless Sensor Transmitter



Gh. Bouzid, H. Trabelsi, Z. Elabed and M. Masmoudi
 
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ABSTRACT

This study presents a modulator design and implementation for a wireless sensor transmitter. The transmitter architecture presented combines a Binary Frequency Shift Keying (BFSK) modulator, an up conversion mixer, a power amplifier and an 863-870 MHz bandpass filter. The BFSK modulator uses the Frequency Hopping Spread Spectrum (FHSS) technique operating in the European ISM band 863-870 MHz. This modulator is intended for short-range wireless applications, such as the wireless sensors network. The modulator generates a 7 MHz wide single-sideband frequency hopped spread spectrum waveform. This modulator is designed using the Direct Digital Frequency Synthesizer (DDFS), which enables us to generate BFSK signal with the hopping frequencies. Low power DDFS architecture is presented. It uses a smaller lookup table for sine and cosine functions compared with existing systems using a minimum additional hardware. The evaluated Spurious Free Dynamic Range (SFDR) of the proposed modulator is -88 dBc. A modulator IC has been designed in AMS 0.35 μ m standard CMOS process technology with a layout chip area of 0.16 mm2. A 20-bit frequency control word gives a tuning resolution of 41.29 Hz at 43.4 MHz sampling rate. This modulator consumes 47.7 μW with a 3V supply at 43.4 MHz.

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Gh. Bouzid, H. Trabelsi, Z. Elabed and M. Masmoudi, 2009. FHSS-FSK Modulator Design and Implementation for a Wireless Sensor Transmitter. Trends in Applied Sciences Research, 4: 1-13.

DOI: 10.3923/tasr.2009.1.13

URL: https://scialert.net/abstract/?doi=tasr.2009.1.13
 

INTRODUCTION

The market for low power, short-range wireless sensor and control technology is expected to show explosive growth during the coming years. The typical applications are home automation, industrial control and monitoring, automatic meter reading and alarms. There are so many applications for this low data rate short-range wireless sensor such as industrial and commercial, home automation, personal computer peripherals, consumer electronics, personal health care and game that should be able to operate for five years under battery energy supply.

Recently developed new standards are under consideration for wireless sensor networking. Examples include Bluetooth (IEEE 802.15.1), UWB (IEEE 802.15.3) and Zigbee (IEEE 802.15.4). Each of these standards is accompanied by limitations for sensor networks. For example, currently available Bluetooth devices show excessive power consumption for sensor network applications (Trung et al., 2006).

The Electronic Communications Committee (ECC) has established new strategic plans for the future use of the 863-870 MHz band for Short Range Devices (SRD) (Electronic Communications Committee, 2002).

Therefore, the 863-870 MHz band, which is available only in Europe, is a good field to test new ideas and concepts toward the development of a low power transceiver for short range and low data rate applications.

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Fig. 1: Wireless sensor transceiver architecture

The direct conversion transmitter has recently attracted widespread attention for its simple architecture and easy integration with the base band circuit, as well as for its low power consumption and low manufacturing costs (Ahmadreza et al., 1998).

Thus, our objective consists in the design of an independent wireless sensor in order to set up a wireless sensor network inside a building. The transmitter is designed for BFSK modulation, with a data rate of 20 kb sec-1. This modulator is designed using the DDFS.

In this study, a low-power technique using a small ROM and 4 pipelined phase accumulator were used to implement DDFS.

Transmitter Architecture The transceiver architecture is presented in Fig. 1. The transmitter part operates as follows: The digital FSK modulator modulates the data and synthesizes in a quadrature outputs a FHSS signals at base band.

A fixed-frequency oscillator up converts these outputs to the ISM band in a single-sideband mixer. With an 866.5 MHz oscillator, in the center of the ISM band either the upper or the lower sideband is selected to place the instantaneous carrier frequency anywhere in the band. The modulator is based on DDFS. The DDFS output frequency needs only to span from 0 to 3.5 MHz to cover the ISM range of 866.5±3.5 MHz.

The digital data is carried by symbol tones at an offset of either ±20 kHz from the carrier frequency. This system can achieve a maximum data rate of 20 kb sec-1 by sending two symbols per hop.

The theoretical study for determining the data rate is presented in the following section.

Data Rate Selection If at each transmission the node sends one full packet, then the overall average power consumption Pd of the transmitter node can be approximated by:

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(1)

where, Ptx is the power radiated from the antenna, Ttx is the time required for each transmission, Twu is the wakeup time of the transmitter (i.e., the time required to start up the circuitry), Pidle is the power dissipated in the idle mode when most of the transmitter functions are off, Pdiss is the non-radiated power dissipated by the transmitter and T is the time interval between two consecutive transmissions. From the Shannon-Hartley theorem, it is known that:

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(2)

where, B is a fixed bandwidth and D is the maximum data rate achievable on an additive white Gaussian noise channel. The term S/N is the signal to noise ratio at the demodulator side (SNRin, dem) and can be related to the signal to noise ratio at the receiver input (SNRin, rec) by:

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(3)

where, NF is the noise factor of the receiver. Suppose that the received signal arrives attenuated by a factor PL(path loss), then:

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(4)

where, NAWGN is the power spectral density of an additive white Gaussian noise channel. Substituting (2) in (4), yields an expression for the transmitted power as a function of all the other parameters:

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(5)

Now the transmission time is defined as:

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(6)

where, Lpacket is the packet length. Substituting (5) and (6) in (1), an approximated formula is obtained for the power dissipated by the transmitter as a function of the data rate. If the receiver has a noise factor of 20 dB, then the overall power consumption, as a function of D and Pdiss appears as shown in Fig. 2 for a packet length of 100 bits. Here each node transmits every 1 min, with a bandwidth of 80 kHz, the channel attenuation is 102 dB, the wake-up time is 1 msec and the Pidle is 10 μW. From this Fig. 2, it is clear that the data rate can be lowered to a certain value. Below some hundreds of bits per second the duty cycle will increase to a point for which, the power dissipated in the transmitter circuitry will dominate, increasing the overall power consumption.

In conclusion, target of 20 kb sec-1 is selected with a balance between the requirements of lower power, bandwidth efficiency favouring closely spaced channels and a BFSK tone frequency that avoids the impact of CMOS flicker noise and DC offset.

Frequency Allocation The transmitter is designed for BFSK modulation, with a data rate of 20 kb sec-1 (Trabelsi et al., 2006). The power spectrum of a BFSK signal is represented in Fig. 3. The transmission bandwidth B of the BFSK signal was calculated to be 80 KHz.

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Fig. 2: Power consumption as a function of data rate and power dissipated by transmitter circuitry

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Fig. 3: Power spectrum of a BFSK signal (bit rate = 20Kbps)

A maximum of 58 channels has been chosen to fulfil FHSS requirement and ETSI regulations (which demand a minimum separation of 25 kHz between adjacent channels) (Electronic Communications Committee, 2002; Trabelsi et al., 2006). Therefore, the separation between adjacent channels has been chosen equal to 40 kHz. The allocation of the 58 channels is shown in Fig. 4.

Modulator Design The modulator is implemented using scalable cells, which have been sized down to the minimum required clocking speed of 43.4 MHz. Frequency is selected with a 20 bit frequency control word to obtain a Fclk/2N frequency control resolution, where N is the number of frequency control bits and Fclk is the sampling frequency of the DDFS/DAC. For Fclk = 43.4 MHz, the smallest frequency resolution is 41.29 Hz. The frequency control word sets the accumulation rate in the phase accumulator, which addresses ROMs containing coefficients of the trigonometric sine and cosine waveforms to produce digital-domain quadrature outputs at the programmed frequency. The choice of internal word length guarantees that in the worse case, imperfections in the DDFS will result in spurious tones of at least -72.6 dBc relative to the fundamental frequency (Yang et al., 2004).

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Fig. 4: Channels allocation in the 863-870 MHz band

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Fig. 5: The Modulator block diagram

The architecture proposed of the modulator system is shown in Fig. 5. Essentially, a modulator consists of a DDFS, a PN code generator and a mixer. The DDFS creates digital samples of a baseband sinusoidal waveform by addressing a sine ROM at a frequency set by a 20-bit control word. The PN code is a random generator code, which corresponds to the hopping patterns. The mixer selects one of the two codes generated by both PN code generators.

The PN code generator and the DDFS used in the modulator are explained in the following sections.

Pn Code Generator In its frequency hopping sequence, the signal hops to a different channel during each hopping period. The discrete hop frequencies are determined by a PN code sequence stored in the memory before the input control register of the DDFS. The carrier frequency hops at 20 hops sec-1 among these 58 channels, according to a pseudo random sequence.

The PN code is a random generator code which has a 20 bits length and works at the rising edge of a clock frequency which is lower than the sampling frequency. At each clock edge the PN code will generate a binary word N (frequency control word), which serves as incremental phase for the DDFS, as shown in Fig. 6. The N binary words are stored in a ROM memory that will be sent to the DDFS at each clock period. The hardware description and design of the PN code generation has been done using the VHDL. Post simulation of the designed modules has been done using the VHDL simulator to verify the description.

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Fig. 6: Simulation results for PN code

DDFS Description The overall architecture of a typical DDFS system is shown in Fig. 7. Essentially, a DDFS consists of a phase accumulator and a sine/cosine generator. The phase accumulator input is a frequency control word (Fcw). The phase accumulator is an overflowing N bit accumulator whose value specifies the instantaneous phase. The rate at which this phase ramp overflows gives the generated frequency which is proportional to Fcw.

The amplitude of a sinusoidal signal is digitally stored in a ROM and is consecutively fetched by the output of an accumulator, which feeds the address line of the ROM (Tierney et al., 1971). The output sine wave produced has the same frequency as the phase ramp rate overflow, which is proportional to Fcw. The output sine samples can be converted to an analog waveform using a digital-to-analog converter (DAC) and a low-pass filter (LPF) (Lee and Park, 2003).

The accumulator input and its word-length determine the output frequency value and resolution, respectively.

The generated frequency Fout is related to the frequency control word and the reference frequency Fclk by:

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where, N is the accumulator word-length (Akram and Swartzlander, 2003).

The two main parts, the phase accumulator and the ROM, of the DDFS are explained in the following sections.

The Phase Accumulator The phase accumulator, shown in Fig. 8, is a 20 bit adder that repeatedly increments the phase angle by Fcw. Therefore, its output increases by Fcw at each clock cycle. At the time n, the phase accumulator output is given by:

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and the sine/cosine generator must compute sin (2Ï€n Fwc/2N) and cos (2Ï€n Fwc/2N).

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Fig. 7: Typical DDFS system

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Fig. 8: The phase accumulator block diagram

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Fig. 9: A conventional pipelined accumulator

A large phase accumulator is frequently used in DDFS for the fine frequency resolution at high clock frequency. However, this large accumulator cannot finish one addition in a small single clock period because of the delay caused by the carry bits propagating during the addition. A typical solution is to pipeline the phase accumulator as m stages of L bits each, such that, mxL = N as shown in Fig. 9. Each adder generates L+1 bits output: L sum bits and one carry output bit. The carry output is latched between successive adders. Every new frequency control word is moved into the pipeline circuits consisting of D-flip-flops (DFF) and delay elements. The speed of the phase accumulator, based on this architecture, can be increased up to m times. For the DDFS implementation, we used a four level pipelined phase accumulator.

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Fig. 10: Block diagram of proposed DDFS

However, the pipeline circuit requires considerable area and power and introduces more frequency switching latency. At the same time, increasing the number of pipelined blocks would increase the loading of the clock network.

The Read Only Memory A first step towards the reduction of sine/cosine generator complexity consists in truncating the least significant bits (LSBs) from the phase accumulator (Fig. 10). This introduces spurious noise in the DDFS outputs (Strollo et al., 2007; Jafari et al., 2005), which should be carefully taken into account in the design phase. Another common approach, usually used to simplify the sine/cosine generator, exploits the quadrant symmetry of trigonometric functions and identities. For a quadrature DDFS, this reduces the task of the sine/cosine generator to the calculation of sine and cosine functions for angles belonging to the interval only. For a single-phase DDFS, sine calculation for phase angles, belonging to the first quadrant, is required. Simple DDFS implementations use a ROM lookup table to calculate trigonometric functions.

One effective method of reducing the ROM size is to exploit the quarter-wave symmetry properties of the sine curve. Thus the quadrant-decode technique is employed in order to generate a full sine wave.

The second MSB is used to determine whether the phase accumulator output has to be inverted and the first MSB determines whether the sine amplitude output of the LUT has to be inverted. This method produces a four-fold decrease in the ROM size.

MODULATOR SYSTEM-LEVEL SIMULATION

Modulator Simulations The most demanding characteristics of modulator are SFDR and output spectrum. The simulation purpose is to determine the design performance of the modulator. The design in Fig. 5 is coded by VHDL, which is then simulated by Modelsim. The VHDL code is then synthesized by Quartus.

Figure 11 shows the modulator output for maximum code. At each clock rising edge (clk1), the PN code will generate a binary word N (frequency control word), which serves as incremental phase for the DDFS. At each DDFS increment (clk2), the modulator will generate a sample of sin and cos, as shown in Fig. 11. At each signal edge (s), the mixer switches between both PN code generators. The output of the modulator for minimum code is presented in Fig. 12. Figure 13 shows the quadrature phase between sine and cosine. We note that if the sine is zero, the cosine is in its maximum and when the sine takes maximum values, the cosine begins to take negative values. Figure 13 shows the transition of sine and cosine signals corresponding to two different codes before and after the inversion.

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Fig. 11: Simulation results for maximum code

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Fig. 12: Simulation results for minimum code

Spurious-Free Dynamic Range (SFDR) The SFDR is defined as the ratio of the desired frequency component amplitude to that of the largest undesired frequency component at the output of a modulator, as shown in Fig. 14. Its value is usually expressed in decibels. An undesired (spurious) frequency component is often called a spur. Modelsim of Mentor and MATLAB of Mathworks are the software tools to perform system-level simulations. Meanwhile, the decimal output data in a 10-bit format are collected. The Fast Fourier Transform (FFT) command of MATLAB is executed to obtain the spectrum as shown in Fig. 14, which illustrates that the spurious performance of the proposed method is as high as -88 dBc. It is far better than any prior works.

The data shown in Table 1 compare the performances of the developed DDFS with recently published state-of-the-art circuits, using CMOS technology, SFDR and clock frequency similar to the ones considered in this paper. The proposed IC exhibits a power dissipation reduction by a factor larger than 10 and a substantial decrease of the maximum clock frequency, with respect to the solutions proposed in (Langlois and Al-Khalili, 2003). The DDFS of (De Caro et al., 2004) dissipates 51% more power and has higher output resolution and SFDR. However, it is faster than our design.

Table 1: Performance and comparison of proposed DDFS
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Fig. 13: Modulator Block simulation results

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Fig. 14:
Spurious performances of the proposed modulator for the 24th code

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Fig. 15: The modulator chip design

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Fig. 16: The modulator chip layout

Chip Implementation The design was implemented using the AMS 0.35 μm CMOS standard cell library, triple metal technology with a linear capacitor. To generate a hardware model from software algorithm some simple logic and arithmetic blocks (such as: multipliers, adders and logic gates) have been used. The DDFS can be built using VHDL description. First, the design was coded in VHDL and verified using NClaunch. Second, the Cadence Ambit tool was used to perform logical synthesis and optimization. Finally, the placement and routing and the Design Rule Check (DRC) were done using, respectively, Cadence Silicon Ensemble and Cadence virtuoso. The chip design is broken down into thirteen major subsystems (Fig. 15).

Simulation results show that the average power dissipated is 47.7 μW at 43.4 MHz. It is interesting to conclude that the DDFS power dissipation is close to 63% of the total power. The power consumption of the PNcode1 and PNcode2 is 17 and 18%, respectively. The power dissipation of the accumulator is not negligible since it requires about 19% of the total power. The power consumption of the lookup tables is as low as 22%.

The chip operates from a nominal 3V power supply. The modulator chip layout, shown in Fig.16, contains 1205052 transistors and has a die size of approximately (0.396x0.396) mm2.

CONCLUSION

In this study, we have presented a novel FHSS-FSK modulator implementation design. First, we have presented a novel method exploiting the quadrant symmetry of trigonometric functions and trigonometric identities for the purpose of reducing DDFS spurious tones. A new DDFS architecture based on this technique was presented. A DDFS has been presented which uses a smaller lookup table for sine and cosine functions and four level pipelined phase accumulator. Furthermore, we described the modulator simulation results, which have been designed using the proposed DDFS. It enabled us to generate BFSK signal with frequency hoping. The design was implemented using a 0.35 μm CMOS technology. It occupies a core area of 0.16 mm2. The entire chip operates at a low supply-voltage of 3 V. Simulation results show that the average power dissipated is 47.7 μW at 43.4 MHz with an 88dBc SFDR.

REFERENCES

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2:  Akram, W. and Jr. E.E. Swartzlander, 2003. Direct digital frequency synthesis using piece-wise polynomial approximation. Proceedings of the Signals, Systems and Computers, 2003 Conference Record of the Thirty-Seventh Asilomar Conference, November 9-12, 2003, Austin, TX, USA., pp: 2237-2241
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