ABSTRACT
Secure, complex and high speed cryptosystem is essential for transmission of information. Attackers can be avoided in application specific hardware. In this study, security is enhanced by Pell equation and chaotic key based algorithm. Chaotic key based algorithm has been widely used for encryption now days. The proposed algorithm is for encryption and decryption of text. VLSI architecture of cryptosystem is proposed for hardware implementation to increase the speed of computation and complexity. Separate hardware increases security and consumes less power.
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URL: https://scialert.net/abstract/?doi=rjit.2013.242.248
INTRODUCTION
There is a need for secure encryption and decryption to protect the valuable information in many applications like military image database, medical imaging etc. Pell equation and chaotic key based algorithm has various cryptographic features independently. Some of the symmetric key algorithms are AES-advanced encryption standard, blowfish, RC4, IDEA. These are well known algorithms and are easily subjected to various attacks. The symmetric key proposed by Murthy and Swamy (2006) can be recovered using a very low complexity known plain text attack. The cryptanalysis technique described by Zheng et al. (2006) and Alvarez et al. (2004) appears difficult but it is less time consuming due to the use of small size key. Sarma and Avadhani (2011) and Mitter and Priya (2012) proposed a method using pell equation alone is of highly insecure and is easily cryptanalysed (Alvarez et al., 2008; Singh and Kaur, 2011). Ismail et al. (2010) proposed a method using two logistic maps which consumes high encryption time and power. The cryptosystem proposed in (Rao et al., 2011; Rao and Gangadhar, 2011) is unreliable because of decryption. Masuda and Aihara (2002) proposed a method (Mitter and Priya, 2012; Singh and Kaur, 2011; Yen and Guo, 2000; Kanso and Smaoui, 2009) using chaotic maps alone didnt ensure authentication. In this study, a new algorithm by combining Pell equation and chaotic key based algorithms is proposed which has increased cryptographic features. Pell equation, a special form of Brahmagupta Bhaskara (BB) equation ensures confidentiality and authentication.
A number of root pairs can be obtained from Pell equation. And the root pairs obtained after decryption ensures that the message is authenticated .A primary symmetric key is used for the root pairs.
Chaos based algorithm has been widely used in encryption and decryption of Text and Image (Alvarez et al., 2004; Mishra and Mankar, 2011; Hamri et al., 2011). Crypto system in VLSI is designed for encrypting and decrypting the text and even the encryption and decryption keys are stored in it. The proposed system is an application specific system. In this study, Pell equation and chaotic key based algorithm is used to provide Secure, complex and high speed cryptosystem for transmission of information in application specific hardware. The proposed algorithm is for encryption and decryption of text using VLSI architecture to increase the speed of computation and complexity.
BB equation and pell equation: One of the Ancient mathematical equation known as Pell Equation ensures authentication. The BB equation is given by Pa2+k = b2. Pell equation is a special form of BB equation when k = 1, the equation is given by:
![]() | (1) |
The input to the equation is the character value P. The fundamental smallest root pairs (a,b) is obtained by trial and error method. From the smallest root pair values number of root pair values are obtained using Brahmagupta Lemma 2 provided P should be a non perfect square integer. Brahmagupta Lemma 2 iterative formula is:
a = 2ab , b = b2+Pa2
A modulo operation with the primary key K1 is performed with the root pairs (a, b) of the equation 1 is found by various methods square of the root pairs. qa = a2 mod K1 and qb = b2 mod K1.The Pell equation for the proposed method is given as:
![]() | (2) |
Logistic equation: The Logistic equation plays a vital role in Encryption and it is sensitive to initial conditions. They possess the property of ergodicity. The Logistic Equation is given as:
![]() | (3) |
where μ is system parameter and the value should be between [3.57, 4] so that it exhibits chaotic behavior.
X (n) is Initial condition chosen between [0, 1]. For an N character, the logistic sequence is obtained as x (0), x (1) x ((N/L)-1) where L = Bit length of key.
PROPOSED METHODOLOGY
Encryption algorithm: Chaotic key based algorithm posses the property of confusion and diffusion. The Binary Representation of the Logistic sequence is considered where
x(i) = b(2Li+0) b(2Li+1) .b(2Li+(2L-1))
The binary representation of x(0) to x((N/L) -1) is b(0) to b(2N-1).
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Fig. 1: | Block diagram of cryptosystem |
The secondary keys K2 and K3 are chosen such that they satisfy the basic criterion:
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where, ci is the binary representation of K2 and di is the binary representation of K3.
The steps involved in Encryption Algorithm are:
• | Step 1: The BB root pairs are obtained by taking the character value as input |
• | Step 2: A Primary secret key K1 is selected and qa and qb is obtained as shown in Fig. 1 |
• | Step 3: By choosing the initial point x(0) and the system parameter μ, the logistic sequence is obtained and the corresponding binary representation is obtained |
• | Step 4: Choose the secondary keys K2 and K3 and j = 0 |
• | Step 5: For an N character the encryption is done in following procedure. The case statement is based on the value of binary representation of Logistic Sequence for(x=0;x<=N-1;x=x+1) for(y=0;y<=N-1;y=y+1) Case (2b(j)+b(j+1)) |
• | Case 3: | |
• | qae(x,y) = (qa(x,y)+K2) | |
• | qae(x,y) = qae(x,y) XOR K2 | |
• | qbe(x,y) = (qb(x,y)+K2) | |
• | qbe(x,y) = qbe(x,y) XOR K2 |
• | Case 2: | |
• | qae(x,y) = (qa(x,y)+K2) | |
• | qae(x,y) = qae(x,y) XNOR K2 | |
• | qbe(x,y) = (qb(x,y)+K2) | |
• | qbe(x,y) = qbe(x,y) XNOR K2 |
• | Case 1: | |
• | qae(x,y) = (qa(x,y)+K3) | |
• | qae(x,y) = qae(x,y) XOR K3 | |
• | qae(x,y) = qae(x,y) XOR K3 | |
• | qbe(x,y) = (qb(x,y)+K3) |
• | Case 0: | |
• | qae(x,y) = (qa(x,y)+K3) | |
• | qae(x,y) = qae(x,y) XNOR K3 | |
• | qbe(x,y) = (qb(x,y)+K3) | |
• | qbe(x,y) = qbe(x,y) XNOR K3 | |
• | j=j+2 | |
• | Two Encrypted characters qae and qbe are obtained |
Decryption algorithm: The decryption algorithm is reverse of encryption algorithm. The Encrypted character qabe is the input to Decryption Algorithm.
• | Step 1: Using the same initial point x(0) and system parameter μ, the logistic sequence is obtained and the corresponding binary representation is obtained |
• | Step 2: Obtain the Symmetric secondary Keys K2 and K3 and set j = 0 |
• | Step 3 : For N character the decryption is done in following procedure for(x=0;x<=N-1;x=x+1) for(y=0;y<=N-1;y=y+1) case(2b(j)+b(j+1)) |
• | Case 3: | |
• | qa(x,y) = qae(x,y) XOR K2 | |
• | qa(x,y) =( qa(x,y)-K2) | |
• | qb(x,y) = qbe(x,y) XOR K2 | |
• | qb(x,y) =( qb(x,y)-K2) | |
• | P(x,y) = (qa(x,y))-1(qb(x,y)-1) mod K1 |
• | Case 2: | |
• | qa(x,y) = qae(x,y) XNOR K2 | |
• | qa(x,y) =( qa(x,y)-K2) | |
• | qb(x,y) = qbe(x,y) XNOR K2 | |
• | qb(x,y) =( qb(x,y)-K2) | |
• | P(x,y) = (qa(x,y))-1(qb(x,y)-1)mod K1 |
• | Case 1: | |
• | qa(x,y) = qae(x,y) XOR K3 | |
• | qa(x,y) =( qa(x,y)-K3) | |
• | qb(x,y) = qbe(x,y) XOR K3 | |
• | qb(x,y) =( qb(x,y)-K3) | |
• | P(x,y) = (qa(x,y))-1(qb(x,y)-1) mod K1 |
• | Case 0: | |
• | qa(x,y) = qae(x,y) XNOR K3 | |
• | qa(x,y) =( qa(x,y)-K3) | |
• | qb(x,y) = qbe(x,y) XNOR K3 | |
• | qb(x,y) =( qb(x,y)-K3) | |
• | P(x,y) = (qa(x,y))-1(qb(x,y)-1) mod K1 | |
• | j = j+2 | |
• | Finally the original character value of the text is obtained. (qa(x,y))-1 |
VLSI architecture: The parallel processing procedure is adopted for VLSI Architecture. In this a parallel in parallel out register, adder, multiplier, comparator, subtraction, modulo operator, xor operator, modulo inverse operator are used. Based on the number of characters N encryption and decryption process is done in parallel. The encryption and decryption of data are done parallely. The architecture of encryption process and decryption process is shown in Fig. 2, 3.
![]() | |
Fig. 2: | Architecture of encryption process |
![]() | |
Fig. 3: | Architecture of decryption process |
Table 1: | Encryption result |
![]() | |
Table 2: | Decryption result |
![]() | |
RESULTS AND DISCUSSION
The proposed Encryption algorithm is implemented on a text and the encrypted and decrypted outputs are shown in Table 1 and 2, respectively.
The Primary key K1 = 35491, secondary keys K2 = 45678, K3 = 32418. The system parameter μ =3.87 and x (0) = 0.87. The key size is 16 bits. The proposed algorithm is for any key size. Based on the key size the output bit varies and the chaotic binary sequence bits also vary.
CONCLUSION
A secure cryptosystem based on Pell equation (Sarma and Avadhani, 2011) and chaotic key based algorithm is proposed in this paper. Also hardware architecture of cryptosystem is designed in VLSI using Verilog and simulated using ModelSim Software. The Proposed algorithm is highly secure in terms of authentication, data integrity and confidentiality (Alvarez et al., 2008, Ismail et al., 2010). Hardware Implementation of the proposed cryptosystem in VLSI consumes low power and less time for encryption and decryption (Rao and Gangadhar, 2011). Application specific Hardware avoids attackers and increases security.
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