Research Article
FPGA Implementation of Low Power Digital QPSK Modulator Using Verilog HDL
Department of Electrical, Electronic and System, Faculty of Engineering and Built Environment, University Kebangsaan Malaysia (UKM), 43600 Bangi, Selangor, Malaysia
Mohd Alauddin Mohd Ali
Department of Electrical, Electronic and System, Faculty of Engineering and Built Environment, University Kebangsaan Malaysia (UKM), 43600 Bangi, Selangor, Malaysia
Hilmi Sanusi
Department of Electrical, Electronic and System, Faculty of Engineering and Built Environment, University Kebangsaan Malaysia (UKM), 43600 Bangi, Selangor, Malaysia
Sawal Md. Ali
Department of Electrical, Electronic and System, Faculty of Engineering and Built Environment, University Kebangsaan Malaysia (UKM), 43600 Bangi, Selangor, Malaysia
anitha Reply
I read the paper, I need a help for DDS to generate sine & cosine i am doing the project, So i need to generate sine and cosine what you implemented in your paper. I need your guideline to write verilog code for dds to generate sine and cosine.