The Future of Non-planar Nanoelectronics MOSFET Devices: A Review
Munawar A. Riyadi,
Jatmiko E. Suseno
This study was focused on the evaluation of present development of nanoelectronic devices and the projection of future devices, ultimately for non-planar geometry. The recent scaling of IC technology was limiting the employment of conventional, planar structure, thus implies in the wake of the research in non-classical architecture. The present status of extended planar silicon devices, including the insertion of high-k dielectric, metal gate and SOI MOSFET in the recent manufacturing process is elaborated. The alternative path in the enhancement of IC device performance, merely in the sub-50nm dimension is shown, with the role of double gate MOSFET and non-planar structure devices, including vertical FETs, is expected to take greater share, as well as several emerging nanostructures. The possibility to implement the non-planar devices generation heavily depends on the maturity of each technology and the ability to clear the obstacles in processing.
Received: March 10, 2010;
Accepted: May 19, 2010;
Published: July 14, 2010
The progress of semiconductor electronics devices has been marked by the rapid
improvement of performance and low cost application, along with the tremendous
down-scaling of the transistor size, mainly for the channel length. The scaling
of Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) device as the
main device in electronic circuits has led to increasing performance in electronic
systems with more features and higher processing speed, while the performance-to-cost
ratio is also rising. Moores Law predicted that the transistor density
on Integrated Circuit (IC) would be doubled every two years, which drives the
great development in semiconductor industries (Moore, 1995;
Schaller, 1997). It is expected that the prediction
will still valid for the next decade, according to the latest International
Technology Roadmap for Semiconductors (ITRS, 2009).
Recently, Intels commercial silicon process has employed 45 nm MOSFET
technology (Intel, 2004) and soon will be in full production
for 32 nm technology (Intel, 2010). However, some challenges
on the conventional lateral MOSFET arose enormously for the nanoscale (Wong
et al., 2005; Oda and Ferry, 2006). The biggest
impact of dimension reduction goes to the lithography which is limited by the
wavelength of light source used in its system. The commercial optical lithography
has resolution of 70 nm using Deep/eXtreme UltraViolet (DUV/XUV) wavelength
(Lin, 2006a), but it is hard to meet the challenge of
smaller geometries. Other lithography techniques exist, such as scanning electron
beam (Cord et al., 2009), immerse (Lin,
2006b) and x-ray lithography (Taur et al., 1997;
Wong et al., 2005), but all contain technical problems
that remain to be solved for smaller resolution, not to mention the very complicated
and sophisticated equipments and facility installment required which dramatically
increase the manufacturing cost and complexity. Other challenges over the channel
scaling are lying on the fundamental physical limitations of the device and
also the presence of short channel effects (SCE), including threshold voltage
(VT) roll-off, increasing leakage current (Ioff) roll-off,
drain induced barrier lowering (DIBL) and rising dissipation power (Pdisp)
(Frank et al., 2001). The presence of the deteriorating
effects has been the key problem that threatens to degrade the performance in
the next generation of devices.
Alternative technologies are essential as well as advanced device physics approach
for continuing the progress in nanoscale. For this purpose, many researches
were conducted extensively in new materials and new device structures. With
the limitation of conventional structure, several innovative devices emerge
as new promising structure with nanoscale gate length dimension in order to
keep pace with Moores Law in maintaining the performance progress. Thus,
this review will be focused on the present state of planar MOSFET devices and
elaboration of non-planar MOSFET architecture, as well as the emerging nanodevices
for channel length down to nanoscale.
PLANAR MOSFET IN NANOSCALE
The planar bulk MOSFET with a symmetrical source and drain region divided by
the channel area has been around for more than four decades and it retains almost
the same basic structure design. For years, the successful development of MOSFET
has been largely dominated by the size shrinking of its physical properties
(Wong et al., 1999; Liu and
Chang, 2009). Initially, all dimensions and also voltages are reduced by
a factor α and the doping is increased by the same factor (originally proposed
by Dennard et al. (1974)). But voltage scaling
has been slow because the subthreshold slope, the OFF current and built-in potentials
are not scalable (Frank et al., 2001). Moreover,
the device widths and wiring dimensions have not been scaled as fast as the
channel lengths. As a result, the scaling strategy is more complex in these
days, when the channel length approaches sub-100 nm (Zeitzoff,
2006). The scaling of MOSFET leads to SCE in its electrical characteristics,
due to the increased electric field in the channel and the unscalable factors
that led to shifting of current-voltage relationship and deteriorate the power
Several techniques were developed to reduce SCE and also maintain superior
device performance in nanometer scale. Figure 1 shows some
improvements of conventional CMOS to reduce unwanted scaling effects. However,
the limits to MOSFET scaling keep approaching. The tox cannot be
less than 1 nm due to higher tunneling current and significant statistical variation
(Yu et al., 2000). Ultra shallow junction tends
to increase parasitic resistance and poses reliability issue between devices
in a batch (Wong et al., 2005). Nevertheless, the
lowering of carrier mobility cannot be avoided in channel of very high impurity
doping, which in turn reduce the drain current. The substrate doping is high
(>1019 cm3) that leakage and tunneling currents are
becoming unacceptable for certain applications (Moers, 2007).
The current scaling rate, if sustained, will release heat at the chips
surface as strong as the suns surface, in this decade (Masahara
et al., 2008). Moreover, the ultimate physical limit of the scaling
is believed to be the distance of atoms in silicon crystals which is around
0.3 nm (Iwai et al., 2006). Thus, up to certain
point, further scaling will be unrealistic and very difficult to predict.
The Silicon on Insulator (SOI) technique was introduced to improve the conventional
MOSFET design. It has been around at least since 1980s and been applied
in AMDs commercial processors (AMD, 2002). Many
fabrication methods has been proposed to for SOI, which was elaborated in length
by (Celler and Cristoloveanu, 2003). By inserting dielectric
below the transistor, it is expected that the problem due to exaggerated field
can be hold, while the fringing capacitance is suppressed, that in turns give
better speed (Yu et al., 2007).
It also improves devices isolation which combines the STI and the back oxide
(Ioannou, 2005). The SOI design goes further by thinning
the body, to achieve fully depleted regime; an attempt to increase the performance.
The Ultra Thin Body (UTB) Silicon on Insulator (SOI) MOSFET could reduce subthreshold
swing near ideal value (60 mV/decade) (Oda and Ferry, 2006).
However, it also contain problem in the power dissipation issue as the heats
resulted by the devices cannot be absorbed by the substrate due to the temperature
resistance of the back oxide, which may affect the operating temperature of
The strained Si layer is another option introduced for increasing the mobility,
which has been applied in recent AMD production (AMD, 2002)
as well as in Intel (Mistry et al., 2007). By
growing epitaxial silicon layer on Si1-xGex layer, the
grown Si lattice constant follows that of the layer beneath and creates energy
which enhances the low field effective mobility μeff and reduces
scattering (Hoyt et al., 2002; Thompson
et al., 2004). The strained Si is strongly correlated with the portion
of Ge in the Si1-xGex, with optimum value found to be
around 15-25% (Olsen et al., 2004). However,
due to higher demand of current drive, the strained silicon is still approaching
its physical limit (Yang et al., 2007). In addition,
some current process techniques in strained Si tend to be less effective with
Other non-classical MOSFET technologies have also been emerged, while retaining
the conventional planar structure. The junction engineering along with source
or drain extension were applied to prevent the charge sharing effect and to
control S/D junction (Wu et al., 1995; Koo
et al., 2003; Muller et al., 2003).
The introduction of new materials was also popular, although the compatibility
with standard CMOS fabrication is an issue. In the recent technology generation,
high-κ gate dielectrics (e.g., zirconia, HfO2 (Verheyen
et al., 2005)) have been implemented as replacement to SiO2
in order to maintain the acceptable dielectric thickness while keeping gate
leakage currents within tolerable limits. Metal gates (Cheng
et al., 1999; Hou et al., 2004) or
dual work function gates (Polishchuk et al., 2001)
have also been re-introduced to avoid the polysilicon depletion effect which
creates unwanted parasitic gate capacitance. However, threshold voltage control
with metal gate and high-κ material has been very challenging, especially
for low threshold voltage devices, mainly because of difficulties in setting
the effective work function at the conduction and valence band edges for n-type
and p-MOSFETs, respectively (ITRS, 2009).
EMERGING NON-PLANAR DEVICE STRUCTURE
The non-planar structures option seems viable to be a contender in prolonging the future progress of MOSFET. While the scaling of the dimension is still seen by most major manufacturers as a cost-effective way to maintain the progress than to invest with completely new technology, the emergence of novel structures have strengthened in recent years. Now that the scaling of the conventional bulk silicon MOSFET starts slowing down, the non-planar device structures become inevitable in continuation of performance improvement.
Double Gate (DG) structure has been considered as a main way to improve the
performance of single gate classical MOSFET. The DG-FET is electrostatically
more robust than the classical MOSFET since both gates act as shields to the
channel so that they suppress field penetration from the gate, which leads to
reducing short-channel effects (low DIBL) (Wong et al.,
1999; Solomon et al., 2003). It produces
close-to-ideal subthreshold slope (60 mV/dec) due to a high gate-to-substrate
coupling and it offers flexible VT control by separation of two gates
(Masahara et al., 2008). Better SCE immunity
implies that DG structures may use low-doped/undoped channels, which reduce
dopant fluctuation problems usually found in very high doping, improves carrier
transport properties of channel and reduces band-to-band tunneling (BTBT) leakage
current near the drain (Schulz et al., 2002;
Cho et al., 2008).
The double-gate FET can be formed on bulk silicon CMOS by connecting the doped
well to the gate (Solomon et al., 2003), but
it is much more effective to use a true insulated gate. As discussed by Frank
et al. ( 2001), stricter requirements for oxide leakage in low power
applications, as well as and subthreshold and substrate tunneling currents,
lead to larger estimates for minimum channel length and boost the application
of DGFET. Moreover, both gates of DGFET may be biased independently to improve
the device control (Schulz et al., 2002). The
threshold voltage can be controlled by this scenario to increase performance
or raised to reduce standby power. The separate biasing can also be used to
achieve increased logic function from a single FET. In the standard configuration,
although a biased well can be used for similar function, it is rarely applied
due to the impact on capacitance, circuit density and leakage current when forward
biased (Solomon et al., 2003).
A projection of the ID-VGS characteristics of single
and double gate FETs is shown in Fig. 2a. The DG-FET provides
sharper slope resulting from the gate coupling advantage, which also gives lower
threshold voltage for a given off-current. This in turn gives higher drive currents
at lower power-supply voltages VDD. It is clearly evident in Fig.
2b for shorter channel length, where the MEDICI-projected DIBL and subthreshold
swing for the DG device are significantly improved relative to those of the
bulk-silicon counterpart (Nowak et al., 2004).
Some DG topologies are shown in Fig. 3. It describes the
current direction relative to the substrate plane and the position between gates.
Type I expresses the lateral DGFET, while Types II and III are vertical double
gate FET (VDGFET) and FinFET, respectively. The comparison of each type is shown
in Table 1. The VDGFET or the FinFET are easier to fabricate
than the lateral DGFET. In the vertical and fin geometries the body thickness
is controlled by lithographic and etching processes, respectively. The gates
must be precisely aligned (to within one quarter of the gate length), to avoid
compromised performance (Wong et al., 1999;
Frank et al., 2001). The feature for self-alignment
between gates is more easily produced by VDGFETs and FinFETs but harder to make
in the lateral double gate FETs. On the other hand, the lateral DG FETs and
FinFET depend heavily on lithography in defining the channel length, thus the
critical problem in the lithography give bigger impact on further device design.
Vertical MOSFET: The vertical structure offers several advantages as
well as challenges over the conventional/planar structure, according to published
results. The main advantage is the possibility to further downscale the device
with relaxed lithography for channel length definition. The channel definition
of vertical MOSFET is achieved using careful layer deposition or other thin
film definitions, in which the lithography is not very critical (Schulz
et al., 2001; Gili et al., 2004;
Moers et al., 2004; Masahara
et al., 2006). The second advantage of vertical MOSFET is that it
could reduce the required space, depending on the application, as well as doubling
the channel width per transistor area.
||(a) Transfer characteristic of MEDICI-predicted performance
of bulk and double-gate MOSFETs and (b) the DIBL and subthreshold swing
for different channel length (Nowak et al., 2004),
(with permission. ©2004 IEEE)
||Double Gate types, according to current direction and the
position of both gates: lateral DG (Type I), Vertical DG FET (Type II) and
FinFET (Type III) (Wong et al., 1999)
This leads to an increase of packing and integration density and drive current
as compared to the planar MOSFET (Moers, 2007; Ertosun
et al., 2008). Other important advantage is the prospect of having
easier implementation of double/multiple gates formation in the structure than
in conventional MOSFET, added with the possibility to make self-aligned gates
accordingly (Masahara et al., 2005; Cho
et al., 2008) which directly affect the performance, as previous
Conventional MOSFET has a symmetric structure of source and drain related to
the channel region. In the vertical structure, there is a slight difference
in device performance, depending on whether it is Source on Top (SOT) or drain
(DOT), as revealed by some reports (Gili et al.,
2006a). Another issue is the control of excessive overlap capacitance of
gate over source and drain (Schulz et al., 2001;
Hall et al., 2004). The definition of source
and drain in one side and the deposition of gate material without proper aligning
in vertical direction by and large lead to this crucial problem.
Vertical MOSFETs are commonly fabricated using layer epitaxy, ion implantation
and solid source diffusion methods (Fig. 4). Generally, the
epitaxy growth methods (Behammer et al., 1996;
Risch et al., 1996; Fink
et al., 2000; Jayanarayanan et al., 2006)
produce sharp junction, easily crafted to get sub-nm channel and requires simpler
step in making pillar and gate.
|| Comparison of double gate structure variations, from Fig.
However, its low throughput and high overlap capacitance are major problems,
added with floating body effect conceded, which leads to degraded performance.
The solid source diffusion techniques (Hergenrother et
al., 2002; Liu et al., 2004) provide
better self-aligned S/D extensions via sacrificial deposited layer but in a
complex process and it sets thermal budget limitation for following processing
steps due to out-diffusion concern. Both previous methods lacks from CMOS processing
compatibility due to different layer sequences for n and p-channels. On other
hand, the implantation methods (Mori et al., 2002;
Schulz et al., 2002; Gili
et al., 2006b; Saad and Ismail, 2008) offer
easy self alignment (both for S/D extension and also for multi gate formation)
and also maintains CMOS compatible possibility. It is also possible to do selective
implantation by masking the unwanted area with resist layer. However, tight
junction control is needed in defining the channel. It also has a probable defect
by high energy implant (Table 2).
Parasitic overlap capacitance problem is a drawback in most vertical DGFET
structure. A method of sacrificial polysilicon oxidation (Fig.
5) was proposed to reduce the overlap problem (Cho et
al., 2008). Another technique by formation of fillet local oxidation
(FILOX) above source/drain region (Fig. 6a, b)
was successfully introduced to reduce the problem (Gili
et al., 2004; Hall et al., 2004).
Subsequently this work was enhanced by other works such as by incorporating
dielectric pocket (Donaghy et al., 2004; Gili
et al., 2005; Jayanarayanan et al., 2006;
Riyadi et al., 2008a) or by introducing Oblique
Rotating Implantation (ORI) method (Riyadi et al.,
2008b; Saad and Ismail, 2008).
|| Performance comparison of several published data using implantation
|| Vertical MOSFET fabrication methods (Schulz
et al., 2001), (with permission ©2001 IEEE)
||Overlap capacitance reduction technique proposed by
Cho et al. (2008): (a) Si pillar. (b) Oxidation or LTO deposition.
(c) N+ -doped poly-Si deposition. (d) Oxidation until the top poly-Si is
fully consumed. (e) HF dip, remaining poly-Si acts as a hard mask. (f) Sacrificial
oxidation. (g) HF dip, gate oxidation. (h) Gate polydeposition. (©2008
IEEE, with permission)
||The combination of FILOX and ORI techniques: (a) spacer is
formed on the sidewall, (b) oxidation to form FILOX and (c) the ORI to improve
the doping of source/drain region
While the ORI method (Fig. 6c) suggests good tendency in
producing vertical MOSFET, by combining the benefit of the fully depleted feature
in this compatible process (Riyadi et al., 2009),
a better device performance is revealed while keeping the possibility to further
scaling, as shown in. In the Fully Depleted (FD) DG FET, the majority carrier
concentration in the channel region is depleted when a certain gate voltage
is applied. This phenomenon provides reduced junction capacitance and also offers
near ideal subthreshold swing with reduced kink effect (Xiangli
et al., 2003). The FD DGFETs have higher punch through immunity in
the short gate length region, compared to the conventional single gate MOSFET
case. This device is also able to eliminate Floating Body Effect (FBE) (Pretet
et al., 2002; Hakim et al., 2006).
In Partial Depleted (PD) devices, floating body can charge up which will eventually
cause dc effects such as premature breakdown and increasing subthreshold swing
at high drain bias. It could also ignite parasitic bipolar mechanism, as the
majority carrier in body is pulled down and concentrated in the bottom and later
cause greater leakage current over the body. Therefore, the tendency of further
device development is toward the fully depleted configuration and the drive
toward this settlement is stronger for nanocale device.
Multiple-gate FET: Several multiple-gate FET concepts which are mostly
based on SOI technology have been around, e.g. triple-gate FETs, Ω/Π-gate
and gate-all-around (Jong-Tae and Colinge, 2002; Colinge,
2004; Poiroux et al., 2005; Im
et al., 2008), as shown in Fig. 7. These devices
offer a higher current drive per unit silicon area than conventional MOSFETs.
In addition they offer optimal short-channel effects (reduced DIBL and subthreshold
slope degradation). A variant of multiple-gate FET, gate-all-around (GAA) FET
(Song et al., 2006) is often considered as quasi-1D
devices. Its physics are similar to the nanowire, with the main channel in inner
material surrounded by the dielectrics and gate material, from which the surrounded-gate
FET name comes. The construction of GAA FETs is easily obtained with vertical
FET-like processing, as the dielectric and gates can be grown around the cylindrical
or rectangular channel with homogeneous thickness, while in horizontal scheme,
the homogeneous thickness of dielectrics are hard to fabricate. The cylindrical
GAA FETs is particularly of interest due to its uniform field in the channel,
offering the simplicity in design and modeling.
The multiple-gate FETs are able to provide higher current drive than the double
gate FETs. However, the multiple-gate FET suffers from the practicality of the
fabrication (except for the vertical GAA FET), a drawback that seems to be biggest
obstacle for adoption. Moreover, the double gate structures have the flexibility
to separate the gates (Poiroux et al., 2005),
thus enabling the adjustment of threshold voltage by controlling separating
Emerging nanostructures and materials: In the search for extending the
progress of nanoelectronic devices, materials other than silicon has been under
intense scrutiny. Several candidates have been promoted with the FET-like operation,
e.g., carbon nanotubes (Javey et al., 2003, 2004),
graphene (Grassi et al., 2009), nanowires (Wan
et al., 2009), etc, all in quasi-1D devices. Carbon Nanotube (CNT)
FETs features high carrier mobility and high quasi-ballistic charge carrier
velocity which has the potentials to overcome the short channel effects. However,
several challenges lay on its development as it requires process for gate and
dielectric to wrap the channel, similar to horizontal nanowire, which is hard
to get in lateral direction. It is also extremely difficult to produce reliable
single wall semiconducting nanotubes and control the band gap energy. With very
different material properties than Si, controlling the carrier type and density
cannot be made as in regular FET.
|| Several multiple-gate FET concepts
The control of chirality in carbon nanotube and the growth of nanotube position
are another big obstacle. Nanowire FETs with various materials offer an appealing
approach to scaling MOSFETs with features similar to CNT FETs. However, it poses
challenges related to its growth and manufacturing process, added with the reliability
issue, whilst contain severe parasitic resistances and capacitances. Graphene
nanoribbon (GNR) is also under intense research nowadays. It is used as a channel
replacement material with prospective properties to be an alternative for silicon.
Unfortunately, the technology has not reach a mature stage while facing several
important challenges. Unless several materials and process challenges have been
overcome, these alternatives may not offer sufficient device gain to be competitive
in mass production, at least for next decade.
The recent progress of nanoelectronic devices has revealed many novel devices
under consideration. Even though some devices have achieved experimental results
comparable with some of the best silicon FETs, these devices have yet to show
electrical characteristics beyond the basic, functional level (Wong,
2005). In several years from now, the planar MOSFET, combined with high-k
dielectric and coupled with strained layer technology, is expected to maintain
its domination the market, due to the fact that the manufacturers still attempt
to exploit their existing manufacturing capabilities and seem reluctant to adopt
new technology. However, the double- and multi-gate MOSFET scaling is superior
to recent planar MOSFET and also to UTB FD MOSFET scaling, thus the double and
multi-gate device is projected as the ultimate MOSFET. The role of double gate
MOSFET and non-planar will take greater share, as this technology become mature
and the risk are more understandable in near future.
On the other hand, several issues on fabrication in adoption route to standard
fabrication have to be solved for every other technology. Figure
8 indicates the projection for the first year of full scale production for
future nanoelectronic devices by ITRS, which reflect the degree of complexity
in fabrication for each technology. New MOSFET structures, starting with UTB-SOI
MOSFETs and followed by multi-gate MOSFETs, will be implemented soon. The next
generation devices, e.g. carbon nanotubes, graphene, spin transistor etc are
promising, due to their performances shown by many researches. However, the
processing issues force them to take longer step to be main devices for nanoelectronics.
||Projection for the first year of full scale production for
future nanoelectronic devices (ITRS, 2009)
In addition, different companies may take different timing in extending planar
bulk and then switching to the advanced technologies, depending on their technological
strengths. Understanding the reliability issues for all these innovations in
a timely manner is very crucial and a great task that remains to be solved.
The authors would like to acknowledge the financial support from E-Science grant (Vot. No 79178) of Malaysias Ministry of Science, Technology and Innovation (MOSTI). The authors express their gratefulness to the Research Management Centre (RMC) of UTM for providing research environment in conducting this work.
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