The main difficulty of low-voltage switched-capacitor (SC) circuit design is the driving voltage of the input CMOS switches. Two conventional approaches for low-voltage SC design using standard CMOS technologies are currently implemented. The first one is the bootstrapping method (Dessouky and Kaiser, 2001) in order to generate higher clock voltages to drive the gate voltage of the input switches, although the existence of on-chip high voltages is a danger for deep-submicrometer CMOS processes (Guan et al., 2001). The second one is the switched-opamp method (Sauerbrey et al., 2002; Cheung et al., 2002). The opamp in the integrator is turned on and off to transfer voltage signals to the next integrator stage, so no input switch is required to sample the input voltage. Switched opamp method is a real low-voltage SC circuit, but it is not suitable for high-speed SC circuit applications due to turning on/off time of the opamp. Another example of non switched mode approach is the GM-C filters which are designed and presented in low voltage applications (Garcia-Ortega et al., 2007). Recently the auto-zeroed integrator (AZI) and its application for low-voltage SC circuits was reported by Wang and Embabi (2003), where the basic AZI circuit (Bidari et al., 1999) was modified for the design of low-voltage and high-speed SC without bootstrapped clock voltage. Based on the previous study reported by Wang and Embabi (2003), here a two mode clock controlled opamp is utilized in order to reduce the power consumption and settling time of the auto-zeroed integrator circuit. First the basic modified AZI block and the new opamp structure are explained. Then a band-pass filter with centre frequency of 1 MHz and clock frequency of 6 MHz based on the above idea is designed, explained and compared to the previous study. Finally a new structure for implementation of the low-pass filter using AZI is presented. The capacitor coupling input in the conventional AZI circuits does not allow designing of low-pass filters. This short coming is solved by designing an additional input stage. Based on this design a fourth order Chebyshev filter with pass frequency of 600 kHz and clock frequency of 6 MHz is designed and simulated.
IMPROVED AZI CIRCUIT
The high speed low-voltage SC filter can be realized by cascading of AZI blocks. Figure 1 shows the basic differential AZI block. The complete description of the circuit is explained by Wang and Embabi (2003) and Rashtian and Hashemipour (2006). Equation 1 shows the mathematical sequence in time domain and Eq. 2 shows the Z-domain transfer function of this circuit if the input of the AZI circuit comes from the output of another AZI block.
It is important to notice that all switches in this circuit are nMOS transistors whose sources are connected to the common-mode voltage VCM and the gates are stimulated at the supply voltage VDD, which is expressed as VGS(on) = VDD-VCM. This means that VGS is not signal dependent, so charge injections and clock feed-through are cancelled in fully differential structure. If we assume that VCM = 0.5V to keep a reasonable output swing range to satisfy the requirement of VGS>VTH to turn on a switch (VTH ≈ 0.6V), the supply voltage should be VDD > VTH + VCM > 1V. This explains why AZI can work at 1.5 V in 0.25 μm CMOS technology.
In phase (φ1) in Fig. 1, the output and input of the op-amp are connected together by the action of switches (M6 and M8) and the final value of the output voltage is a dc voltage (VCM). Doing so, the linear action of the opamp is not critically essential and setting of the output voltage at VCM can be done by external switches. In this approach the output stage of the opamp is operated in two current mode levels by the current steering action of the transistors M5B-M8B as shown in Fig. 2.
The W/L ratio of the current steering transistors is ten times greater than M5-M8. The current steering mode is controlled by transistors M5C-M8C. In the integration phase (φ2), the output stage current is normal but in the other
phase (φ1) it is under low current condition. This can be called
as pseudo switched opamp configuration with an improved characteristic of power
consumption without speed reduction characteristics of switched opamps. In the
phase (φ1) the output voltage is set to VCM by the
non-linear action of nMOS switches M17 and M18. Unlike
the switched opamp technique, the nonlinear action of these switched transistors
and the linear action of opamp without current steering transistors i.e., (M5B-M8B)
will result in the same final steady state value with reduced power consumption.
||Basic auto zeroed integrator circuit
It means that the nMOS switches M17 and M18 are only
used to reduce the settling time. The fast action of common mode feedback is
critically important in high speed switched capacitor circuits (Hernandez-Garduno
and Silva-Martinez, 2006) (Choksi and Carley, 2003). In this study, a unique
dynamic common-mode detection circuit (C3~C6) working
at 1.5 V without any signal-dependent switch is utilized. The detected common-mode
voltage is compared to VCM through M9 and M10.
The result is fed back to the input stage of the opamp through a current mirror.
Both C3 and C4 are discharged in φ1 (the
integrating phase) because the outputs are auto-zeroed by M17 and
M18. In φ2, output voltages are sampled by C3
and C4 and integrated with C5 and C6. These
four capacitors and the switches perform as an RC voltage divider.
BAND-PASS FILTER DESIGN
Figure 3 shows the schematic circuit of the band-pass filter (Wang and Embabi, 2003) with capacitor values of (C1 = 0.5, C2 = 2.31, Ci1 = 1.95, Ci2 = 2.15, Cc = 0.3, Cf = 1.92) pF. The clock frequency is set to 6 MHz with centre frequency of 1MHz and Q = 8.
Assuming the output of the first and second stage to named V1 and V2, respectively then:
From Eq. 3 and 4 the z-domain transfer function is given by 5:
Output of the improved circuit and the previous study (Wang and Embabi, 2003) are compared in Fig. 4 at an input frequency of 1 MHz and Vp-p = 1.2 V. For assessment of fall time improvement in proposed method a small part of Fig. 4 is magnified in Fig. 5.
As shown in Fig. 5, the fall time is improved by the non-linear
action of switches (M17 and M18) in the proposed opamp.
Simulated results show a remarkable reduction (~32%) in the power consumption
of this circuit compared to previous study.
||Band-pass SC filter
||Simulated output of differential band-pass filter at 6 MHz
Figure 6 is acquired by using of more than 100 transient
||Band-pass filter frequency response
LOW-PASS FILTER DESIGN
The input coupling capacitor, which is used in the input of conventional AZI circuits, prevents applying the AZI circuit to be realized as a low-pass filter. This problem is eliminated by the addition of an input circuitry (OP0 and related components) as shown in Fig. 7 where this technique is used in a 2nd order low-pass filter. In φ1 the output of OP0 is set to Vcm and in φ2 OP0 is acting as a buffer with gain of (-1). It is obvious that the correct action of this stage depends on the relative accuracy of resistances and absolute accuracy is not crucially important.
Based on the above idea, Eq. 6 and 7 are
obtained in the output of OP1 and OP2, respectively.
Using the circuit shown in Fig. 7 and cascading them with the capacitor values of (C1 = 0.89, C2 = 0.61, Ci1 = 2, Ci2 = 2, Cc = 1.06 and Cf = 0.89) pF for the first stage and (C1 = 0.69, C2 = 1, Ci1 = 1, Ci2 = 2, Cc = 0.38 and Cf = 0.69) pF for the second stage, a low-pass fourth order Chebyshev filter is realized.
The circuit for the 4th order filter is further simplified by the fact that the designed input stage is no longer necessary for the input of the second cascaded biquad stage. This is due to the fact that the output of the first biquad stage is set to VCM in φ2 inherently. Using the above capacitor values and Eq. 6 and 7 the transfer function in z domain is obtained in 8.
Figure 8 shows the differential output of the designed low-pass
filter with input voltage of 1.2 V p-p and cut off frequency of 600 kHz at the
clock frequency of 6 MHz. Frequency response of the designed filter is shown
in Fig. 9.
||Second order low-pass circuit
||Differential output of the Low-pass filter with 1.2 v p-p
input at 600 kHz
||Low-pass filter frequency response
This plot is drawn using more than 100 HSPICE real time simulation.
The auto zeroed integrator performance is improved by a current steering method
and the application of non-linear characteristics of the switched transistors.
Based on this method, a band-pass filter with centre frequency of 1 MHz and
clock frequency of 6 MHz with quality factor of 8 is designed and simulated.
A ~32% reduction in power consumption and a reduction in fall time are also
observed. The short come of the AZI circuit in the realization of switched capacitor
low-pass filter has been overcome by addition of an input circuitry. Based on
this improvement, a low-pass 4th order filter with cut off frequency of 600
kHz and sampling frequency of 6 MHz with differential output swing of 1.4 volt
with 1.5 volt supply is designed and simulated using 0.25 μm technology.