INTRODUCTION
The main difficulty of lowvoltage switchedcapacitor (SC) circuit design is the driving voltage of the input CMOS switches. Two conventional approaches for lowvoltage SC design using standard CMOS technologies are currently implemented. The first one is the bootstrapping method (Dessouky and Kaiser, 2001) in order to generate higher clock voltages to drive the gate voltage of the input switches, although the existence of onchip high voltages is a danger for deepsubmicrometer CMOS processes (Guan et al., 2001). The second one is the switchedopamp method (Sauerbrey et al., 2002; Cheung et al., 2002). The opamp in the integrator is turned on and off to transfer voltage signals to the next integrator stage, so no input switch is required to sample the input voltage. Switched opamp method is a real lowvoltage SC circuit, but it is not suitable for highspeed SC circuit applications due to turning on/off time of the opamp. Another example of non switched mode approach is the GMC filters which are designed and presented in low voltage applications (GarciaOrtega et al., 2007). Recently the autozeroed integrator (AZI) and its application for lowvoltage SC circuits was reported by Wang and Embabi (2003), where the basic AZI circuit (Bidari et al., 1999) was modified for the design of lowvoltage and highspeed SC without bootstrapped clock voltage. Based on the previous study reported by Wang and Embabi (2003), here a two mode clock controlled opamp is utilized in order to reduce the power consumption and settling time of the autozeroed integrator circuit. First the basic modified AZI block and the new opamp structure are explained. Then a bandpass filter with centre frequency of 1 MHz and clock frequency of 6 MHz based on the above idea is designed, explained and compared to the previous study. Finally a new structure for implementation of the lowpass filter using AZI is presented. The capacitor coupling input in the conventional AZI circuits does not allow designing of lowpass filters. This short coming is solved by designing an additional input stage. Based on this design a fourth order Chebyshev filter with pass frequency of 600 kHz and clock frequency of 6 MHz is designed and simulated.
IMPROVED AZI CIRCUIT
The high speed lowvoltage SC filter can be realized by cascading of AZI blocks. Figure 1 shows the basic differential AZI block. The complete description of the circuit is explained by Wang and Embabi (2003) and Rashtian and Hashemipour (2006). Equation 1 shows the mathematical sequence in time domain and Eq. 2 shows the Zdomain transfer function of this circuit if the input of the AZI circuit comes from the output of another AZI block.
It is important to notice that all switches in this circuit are nMOS transistors whose sources are connected to the commonmode voltage V_{CM} and the gates are stimulated at the supply voltage V_{DD}, which is expressed as V_{GS}(on) = V_{DD}V_{CM}. This means that V_{GS }is not signal dependent, so charge injections and clock feedthrough are cancelled in fully differential structure. If we assume that V_{CM }= 0.5V to keep a reasonable output swing range to satisfy the requirement of V_{GS}>V_{TH} to turn on a switch (V_{TH} ≈ 0.6V), the supply voltage should be V_{DD} > V_{TH} + V_{CM} > 1V. This explains why AZI can work at 1.5 V in 0.25 μm CMOS technology.
In phase (φ_{1}) in Fig. 1, the output and input of the opamp are connected together by the action of switches (M6 and M8) and the final value of the output voltage is a dc voltage (V_{CM}). Doing so, the linear action of the opamp is not critically essential and setting of the output voltage at V_{CM} can be done by external switches. In this approach the output stage of the opamp is operated in two current mode levels by the current steering action of the transistors M_{5B}M_{8B} as shown in Fig. 2.
The W/L ratio of the current steering transistors is ten times greater than M_{5}M_{8}. The current steering mode is controlled by transistors M_{5C}M_{8C}. In the integration phase (φ_{2}), the output stage current is normal but in the other
phase (φ_{1}) it is under low current condition. This can be called
as pseudo switched opamp configuration with an improved characteristic of power
consumption without speed reduction characteristics of switched opamps. In the
phase (φ_{1}) the output voltage is set to V_{CM} by the
nonlinear action of nMOS switches M_{17} and M_{18}. Unlike
the switched opamp technique, the nonlinear action of these switched transistors
and the linear action of opamp without current steering transistors i.e., (M_{5B}M_{8B})
will result in the same final steady state value with reduced power consumption.

Fig. 1: 
Basic auto zeroed integrator circuit 
It means that the nMOS switches M_{17} and M_{18 }are only
used to reduce the settling time. The fast action of common mode feedback is
critically important in high speed switched capacitor circuits (HernandezGarduno
and SilvaMartinez, 2006) (Choksi and Carley, 2003). In this study, a unique
dynamic commonmode detection circuit (C_{3~}C_{6}) working
at 1.5 V without any signaldependent switch is utilized. The detected commonmode
voltage is compared to V_{CM} through M_{9} and M_{10}.
The result is fed back to the input stage of the opamp through a current mirror.
Both C_{3} and C_{4} are discharged in φ_{1} (the
integrating phase) because the outputs are autozeroed by M_{17} and
M_{18}. In φ_{2}, output voltages are sampled by C_{3}
and C_{4} and integrated with C_{5} and C_{6}. These
four capacitors and the switches perform as an RC voltage divider.
BANDPASS FILTER DESIGN
Figure 3 shows the schematic circuit of the bandpass filter (Wang and Embabi, 2003) with capacitor values of (C_{1 }= 0.5, C_{2} = 2.31, C_{i1 }= 1.95, C_{i2} = 2.15, C_{c} = 0.3, Cf = 1.92) pF. The clock frequency is set to 6 MHz with centre frequency of 1MHz and Q = 8.
Assuming the output of the first and second stage to named V_{1} and V_{2}, respectively then:
From Eq. 3 and 4 the zdomain transfer function is given by 5:
Output of the improved circuit and the previous study (Wang and Embabi, 2003) are compared in Fig. 4 at an input frequency of 1 MHz and V_{pp} = 1.2 V. For assessment of fall time improvement in proposed method a small part of Fig. 4 is magnified in Fig. 5.
As shown in Fig. 5, the fall time is improved by the nonlinear
action of switches (M_{17} and M_{18}) in the proposed opamp.
Simulated results show a remarkable reduction (~32%) in the power consumption
of this circuit compared to previous study.

Fig. 3: 
Bandpass SC filter 

Fig. 4: 
Simulated output of differential bandpass filter at 6 MHz
clock frequency 
Figure 6 is acquired by using of more than 100 transient
simulation results.

Fig. 6: 
Bandpass filter frequency response 
LOWPASS FILTER DESIGN
The input coupling capacitor, which is used in the input of conventional AZI circuits, prevents applying the AZI circuit to be realized as a lowpass filter. This problem is eliminated by the addition of an input circuitry (OP_{0 }and related components) as shown in Fig. 7 where this technique is used in a 2nd order lowpass filter. In φ_{1 }the output of OP_{0} is set to Vcm and in φ_{2} OP_{0} is acting as a buffer with gain of (1). It is obvious that the correct action of this stage depends on the relative accuracy of resistances and absolute accuracy is not crucially important.
Based on the above idea, Eq. 6 and 7 are
obtained in the output of OP_{1} and OP_{2}, respectively.
Using the circuit shown in Fig. 7 and cascading them with the capacitor values of (C_{1} = 0.89, C_{2} = 0.61, C_{i1} = 2, C_{i2} = 2, C_{c} = 1.06 and C_{f} = 0.89) pF for the first stage and (C_{1} = 0.69, C_{2} = 1, C_{i1} = 1, C_{i2} = 2, C_{c} = 0.38 and C_{f} = 0.69) pF for the second stage, a lowpass fourth order Chebyshev filter is realized.
The circuit for the 4th order filter is further simplified by the fact that the designed input stage is no longer necessary for the input of the second cascaded biquad stage. This is due to the fact that the output of the first biquad stage is set to V_{CM} in φ_{2 }inherently. Using the above capacitor values and Eq. 6 and 7 the transfer function in z domain is obtained in 8.
Figure 8 shows the differential output of the designed lowpass
filter with input voltage of 1.2 V pp and cut off frequency of 600 kHz at the
clock frequency of 6 MHz. Frequency response of the designed filter is shown
in Fig. 9.

Fig. 7: 
Second order lowpass circuit 

Fig. 8: 
Differential output of the Lowpass filter with 1.2 v _{pp}
input at 600 kHz 

Fig. 9: 
Lowpass filter frequency response 
This plot is drawn using more than 100 HSPICE real time simulation.
CONCLUSION
The auto zeroed integrator performance is improved by a current steering method
and the application of nonlinear characteristics of the switched transistors.
Based on this method, a bandpass filter with centre frequency of 1 MHz and
clock frequency of 6 MHz with quality factor of 8 is designed and simulated.
A ~32% reduction in power consumption and a reduction in fall time are also
observed. The short come of the AZI circuit in the realization of switched capacitor
lowpass filter has been overcome by addition of an input circuitry. Based on
this improvement, a lowpass 4th order filter with cut off frequency of 600
kHz and sampling frequency of 6 MHz with differential output swing of 1.4 volt
with 1.5 volt supply is designed and simulated using 0.25 μm technology.