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Sleep Transistor Sizing According to Circuit Speed, Silicon Area and Leakage Current in High-Performance Digital Circuit Modules

Ahmet Kucukkomurler and Steven L. Garverick

It is proposed that the power supply of key circuit modules could be gated to achieve significant reductions of leakage current, with minimal costs to circuit speed and die area in 0.25, 0.18 and 0.07 μm technologies. This study describes an extension to power supply gating using body overdrive and gate underdrive, analysis techniques to predict leakage current and performance parameters, a procedure for optimization of the sleep transistor size and simulation results that demonstrate the accuracy of the analysis and advantages of the approach. A leakage current estimation technique has been studied using the Berkeley Predictive Technology Model Parameters. An estimation technique has been verified using ISCAS85 combinational Benchmark test circuits. Finally the optimization algorithm has been verified using these same benchmark test circuits.

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Ahmet Kucukkomurler and Steven L. Garverick, 2007. Sleep Transistor Sizing According to Circuit Speed, Silicon Area and Leakage Current in High-Performance Digital Circuit Modules. Journal of Applied Sciences, 7: 958-964.

DOI: 10.3923/jas.2007.958.964



With the rapid progress in semiconductor technology, chip density and operating frequency have increased, making the power consumption in battery-operated portable devices a major concern. The goal of low-power design for battery-powered devices is to extend the battery service life while meeting performance requirements. Reducing power dissipation is also a design goal for non-portable devices since excessive power dissipation increases packaging and cooling costs and causes potential reliability problems.

Dynamic Power Management (DPM), which refers to a selective, shut-off or slow-down of system modules that are idle or underutilized, has proven to be a particularly effective technique for reducing power dissipation in such systems. Incorporating a dynamic power management scheme in the design of an already-complex system, however, is a difficult process that may require many design iterations and careful debugging and validation.

For the DPM approach to apply, it is required that each system module support at least two power states, ACTIVE and SLEEP. In the ACTIVE state, the module performs computations or provides services, while in the SLEEP state it does not perform any useful computation or service. It simply waits for an event or interrupt signal to wake it. The power consumed in the ACTIVE state is typically much higher than the SLEEP state, but SLEEP power, which depends on leakage current, is dramatically increasing in deep sub-micron technologies.

The goal of the study is to develop algorithms to predict the leakage current of deep sub-micron circuits in the SLEEP state and optimize the design of power supply gating with respect to ACTIVE performance and SLEEP power.



Leakage current in short-channel MOS transistors results from a variety of mechanisms, as shown in Fig. 1 (Wilson, 2003). The most important components of leakage current are I2, I3 and I7, which are weak inversion (sub-threshold), Drain Induced Barrier Lowering (DIBL) and gate oxide tunneling, respectively. Techniques described in this study serve to reduce DIBL-enhanced, sub-threshold leakage current.

Fig. 1: Sources of leakage current in NMOS transistor

Fig. 2: Technology trend for both leakage current

Leakage current estimation is complicated by dependency of both the gate tunneling and sub-threshold currents on the nature of the input vector being applied to the test circuit. This input state dependency of sub-threshold leakage current has been extensively studied and exhibits the so-called stack effect (Siva et al., 2001).

Gate tunneling leakage current also depends on input state and on the device type. PMOS devices demonstrate gate oxide tunneling currents that are approximately one order of magnitude less than those in their NMOS counterparts. Furthermore gate oxide tunneling depends highly on gate oxide material and thickness. Technology trends show that new high-k dielectric materials might resolve VLSI gate leakage problems in the near future. Figure 2 shows total chip dynamic and static power dissipation trend forecasts based on the international technology roadmap for semiconductors (Sung Kim et al., 2003).

Models for CMOS leakage current: Sub-threshold channel current is the dominant leakage mechanism in deep sub-micron CMOS circuits. This VGS/VSG dependence of sub-threshold leakage current is modeled most simply by Eq. 1 and 2 and the exponential dependence on gate voltage is graphically shown in Fig. 3. In Fig. 3, the solid curve is a fit using the simple analytical model with λN and λP equal to 29.82 and 30.83, respectively, while the discrete data points are the result of BSIM SPICE simulation using the 70 nm Berkeley Predictive Technology Model (BPTM). Figure 4 has been used as a test schematic for capturing VGS/VSG dependence of sub-threshold leakage current for PMOS and NMOS transistor W/L = 70/70 nm (BPTM models

Fig. 3: Gate to source voltage dependency on leakage current

Fig. 4: Test schematic of gate to source voltage dependency on leakage current

Fig. 5: Test schematic of drain to source voltage dependency on leakage current



Due to the DIBL effect, there is also an exponential dependence on VDS/VSD. Figure 5 has been used as a test schematic for capturing VDS/VSD dependence of sub-threshold leakage current for PMOS and NMOS transistor (unity width W/L = 70/70 nm). DIBL effect simply modeled by Eq. 3 and 4 and graphically illustrated in Fig. 6.

Fig. 6: Simulated and modeled leakage currents

Fig. 7: Power supply gating using a PMOS transistor

In Fig. 6, the solid curve is a fit using the simple analytical model with αN and αP equal to 2.21 and 3.23, respectively, while the dotted curve is a simulation result produced using BSIM SPICE with the 70 nm BPTM model.



Power supply gating using a PMOS sleep transistor: Here, we use a PMOS sleep transistor to investigate the effectiveness of power supply gating for Digital Module, it is shown on Fig. 7. We picked PMOS transistor as a sleep transistor, this is because the sleep transistor body needs to be biased for the body overdrive technique, which can be achieved standard CMOS process. On the Contrary NMOS sleep transistor requires twin-well process for the body overdrive (Anis et al., 2003).

In this case, however, we note that the effect of inserting the sleep transistor is to reduce the module supply voltage in the SLEEP state to a value virtual VDD that is, in part, determined by the size of the sleep transistor. This reduced leads to a module leakage that is less than that obtained without a sleep transistor.

Fig. 8: Power supply gating using body overdrive

Fig. 9: Power supply gating with gate underdrive

Power supply gating using body overdrive: Power supply gating with body overdrive is a technique that dynamically changes the threshold voltage of the sleep transistor by modifying its body bias (Tschanz et al., 2003). When a reverse bias is applied to the body of a transistor, i.e., the body of a PMOS transistor is driven to a voltage that is greater than its source voltage VDD, its threshold voltage is increased. As showed in Fig. 8, the body voltage of the PMOS sleep transistor should be set to VDD during ACTIVE mode to achieve low threshold voltage and low on-resistance and set to during SLEEP mode to achieve high threshold voltage and low leakage.

Power supply gating using gate underdrive: As indicated in the Fig. 9, gate underdrive is implemented similar to body overdrive except that the level shifter is attached to the gate of the sleep transistor rather than its body. Gate underdrive reduces sub-threshold leakage current much more effectively than body overdrive, but there is the danger of damage to the gate oxide if excessive underdrive is used.

Fig. 10: Model for propagation delay and internal in ACTIVE mode

Calculation of propagation delay in ACTIVE mode: When the circuit is ACTIVE, propagation delays in the module will be increased due to the non-zero on-resistance of the PMOS sleep transistor, as discussed with the aid of Fig. 10. During each low-to-high transition within the circuit module, a surge of current is drawn from the sleep transistor, creating a voltage drop and reducing the supplied VDD to an internal level . Since this circuit node will typically have a large capacitance, the current surges produced by many logic gates at different instants in time will be filtered to produce a dc voltage


where RON is the on-resistance of the sleep transistor, which is inversely proportional to sleep transistor width WS and CM is the total capacitance of switching nodes in the module and f is the average switching frequency.

The reduced supply voltage determines the on- resistance of the transistors within the circuit module and propagation delay is proportional to on-resistance. Since tPD RON 1/(VDD – |VT|), where VT is the threshold voltage of the MOS transistor, the relative propagation delay of the module with sleep transistor is


In order to calculate , the on-resistance of the sleep transistor will be modeled using RON = 1/[(W/L)S μp Cox (VDD – |VT|)]. Substitution into Eq. 2-5 yields:


Fig. 11: Model for internal VDD and propagation delay versus sleep transistor size

where (W/L)S is the sleep transistor size, μp Cox are process parameters and VT is the threshold voltage of the sleep transistor. Finally, Eq. 7 is substituted into Eq. 6 to determine the relative propagation delay.


The calculation of module capacitance CM is less clear, but can be approximated by summing the gate oxide capacitance, including channel area as well as gate-drain and gate-source overlap, of every transistor in the module. Drain and source capacitance is ignored in this approximation, but this is reasonable since junction capacitance is typically a small fraction of gate capacitance and only a fraction of the source/drain junctions in a static CMOS logic circuit are switched when the output of a logic gate is switched. Thus, we will approximate

(9 )

where, W, L, COX and COL, are channel width, length, gate oxide capacitance and drain-source overlap capacitance respectively. The summation includes all transistors in the logic module.

A typical result of the and propagation delay models is plotted in Fig. 11. In this plot, f, CM, VDD, |VT|, μp (channel mobility) and Cox are equal to 1 GHz, 100 fF, 1 V, 0.1 V, 35 cm2/V sec and 21.6 fF μm-2, respectively, consistent with the 70 nm BPTM. The unit sleep transistor width is 0.07 μm. This plot demonstrates that relative propagation delay approaches one when sleep transistor size is adequately large. In this example, the internal is 0.86 VDD and the propagation delay penalty is 25% when the sleep transistor is 10 units wide.


The ISCAS85 Benchmark test circuits were used to study the behavior of leakage current in complex, static logic circuits and examine the accuracy of the estimation techniques for leakage current and propagation delay. Table 1 summarizes the contents of the circuits in this benchmark set. All of the gates are implemented using static CMOS logic circuits.

We estimate the sub-threshold leakage current for each ISCAS85 benchmark circuit, as a whole, by multiplying the average leakage current contribution from each gate by the number of gates and summing the results. In order to best compare estimated results with SPICE simulations, it is desirable to average across all possible input vector combinations. Such an approach is not practical for large circuits. Instead, we employ a more tractable alternative, choosing 100 input vectors at random and averaging the resulting calculated leakage currents. Such input vectors sets were created using a MATLAB uniformly distributed random number generator. The accuracy of this comparison between estimated results and SPICE simulation was determined by the size of the random input vector sets (Kucukkomurler, 2004).

Simulation of ISCAS85 leakage current using body overdrive and gate underdrive: The leakage current of ISCAS85 benchmark circuits using a PMOS sleep transistor with body overdrive and gate underdrive were simulated, analogous to the previous section and compared to the results with no sleep transistor and with a simple sleep transistor. The body overdrive and gate underdrive was 40%, i.e., 1.4 V for VDD = 1 V for the 70 nm BPTM models. SPICE was used to simulate the leakage current with 100 randomly selected static input vectors applied to the ISCAS85 benchmark circuits. The values obtained by averaging the 100 resulting leakage currents for each configuration are presented in Table 2. Leakage current savings associated with each of the three sleep transistor configurations are promising. The fact that the relative reduction for each configuration is comparable can be attributed to the fact that sleep transistor width has been set to 10% of the total module gate width.

Table 1: ISCAS85 benchmark test circuits estimated and simulated leakage current

Table 2: ISCAS85 simulated leakage currents with and without sleep transistor


Optimization of the sleep transistor depends on the cost function of the parameters: Leakage, width and delay. To better understand the trade off we begin by assigning equal cost for all three parameters and optimize the sleep transistor size accordingly.

where ηpd, ηl, ηw, are waiting cost factors and are the relative propagation delay, leakage current and transistor width, respectively. Waiting cost factors are initially chosen to be equal (ηpd = ηl = ηw = 1/3). However those cost factors can assign to the different values according to importance of the parameter for a specific application. In addition to that optimizing sleep transistor size will perform for underdrive 0, 0.2 and 0.4 V. The optimization calculation have been made for all ISCAS85 test circuits but only some of the results have been plotted and reminder of the results have been tabulated.

Since Ση = 1 and relative parameters have value 1 when compared to the ungated circuit, cost is 1 when the gated circuit has the same quality as the ungated circuit.

Table 3: Optimum sleep transistor width for ISCAS85 test circuits

Fig. 12: Optimum sleep transistor width for underdrive 0 V

Fig. 13: Optimum sleep transistor width for underdrive 0.2 V

Fig. 14: Optimum sleep transistor width for underdrive 0.4 V

A cost less than 1 is an improvement in circuit quality. Leakage current, propagation delay, width overhead normalized relative to the without sleep transistor case and cost function has been plotted. Minimum cost has been determined according to waiting factor parameters. Optimum sleep transistor width for VGS = 0 V is around 10% of the total circuit width. However the optimum sleep transistor is wider when VGS underdrive increases to 0.2 and 0.4 V. Optimum sleep transistor size has been plotted for three cases for the c1355 circuits on Fig. 12-14, respectively. Optimum sleep transistor size for rest of the ISCAS85 test circuit has been tabulated for VGS equal to 0, 0.2 and 0.4 V on Table 3.


Leakage current estimation has been successfully achieved and verified using ISCAS85 test circuits. Sleep transistor size optimization with respect to module propagation delay, leakage current and total transistor width have been achieved and verified using ISCAS85 test circuits. The estimate of propagation delay has been shown to be quite accurate. The estimate of the leakage current is about double simulation when gate underdrive is not used since the leakage of the sleep transistor is comparable to the module. With gate underdrive, the estimate of leakage current is quite accurate.

Anis, M., S. Areibi, M. Mahmoud and M. Elmasry, 2002. Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique. Proceedings of the 39th Conference on Design Automation, New Orleans, Louisiana, USA., June 10-14, 2002, ACM, New York, USA., pp: 480-485.

Kim, N.S., T. Austin, D. Baauw, T. Mudge and K. Flautner et al., 2003. Leakage current: Moore's Law meets static power. Computer, 36: 68-75.
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Kucukkomurler, A., 2004. Leakage power optimization in high-performance digital circuit modules using power supply gating. Ph.D. Thesis, Case Western Reserve University, Cleveland OH, 44106 USA.

Narendra, S., S. Borkar, V. De, D. Antoniadis and A. Chandrakasan, 2001. Scaling of stack effect and its application for leakage reduction. Proceedings of the International Symposium on Low Power Electronics and Design, August 6-7, 2001, Huntington Beach, CA., USA., pp: 195-200.

Tschanz, J.W., S.G. Narendra, Y.B. Ye, B.A. Borkar and S.V. De, 2003. Dynamic sleep transistor and body bias for active leakage power control of microprocessers. IEEE J. Solid-State Circuits, 38: 1838-1845.
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Wilson, R., 2003. Leakage current leads 90-nm rogues. EE Times, OEG20030519S0022.

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