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Research Article
 

Leakage Reduction Techniques of P-type Adiabatic Circuits Based on Dual-threshold and Gate-length Biasing



Cheng Wei, Zhang Xia, Hu Jian-Ping and Han Cheng-Hao
 
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ABSTRACT

The leakage dissipation catches up with the dynamic power consumption gradually and it is becoming an important factor in low-power CMOS circuits. In this work, a p-type complementary pass-transistor adiabatic logic (P-CPAL) using DTCMOS and gate-length biasing techniques is proposed. In order to reduce sub-threshold leakage dissipations, DTCMOS and gate-length biasing techniques are used for the P-CPAL circuits. An ISCAS benchmark circuit using DTCMOS and gate-length biasing techniques is verified. All circuits are simulated with HSPICE using a NCSU 65nm PTM (Predictive Technology Model) process. Results show that both leakage and dynamic dissipations of the P-CPAL circuits with dual-threshold CMOS and gate-length biasing techniques are reduced greatly compared with the normal P-CPAL circuits.

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  How to cite this article:

Cheng Wei, Zhang Xia, Hu Jian-Ping and Han Cheng-Hao, 2013. Leakage Reduction Techniques of P-type Adiabatic Circuits Based on Dual-threshold and Gate-length Biasing. Information Technology Journal, 12: 6513-6518.

DOI: 10.3923/itj.2013.6513.6518

URL: https://scialert.net/abstract/?doi=itj.2013.6513.6518
 

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