This study presents a novel initial frame synchronization scheme of TD-SCDMA system. This algorithm uses the implicit power transition in the special frame structure and introduces a different power ratio detector comparing with the conventional non-coherent algorithms, which makes it less complicated and more reliable. We verify our algorithm by computer simulations and the results show a good and robust performance in a wide range of signal-to-noise ratios (SNRs).
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In order to satisfy the increasing demand for wireless services, 3G mobile communications will be deployed worldwide (Adachi and Sawahashi, 1998; Liu et al., 2003). Among the three 3G standards, TD-SCDMA owns the advantages of low transmission power, high spectrum efficiency and flexibility for asymmetric traffic services (Miya et al., 1998; Li et al., 2005). However, the downlink of TD-SCDMA must be synchronizing all the time, which is difficult in practical systems, such as low cost terminals, repeaters. Moreover, unlike the other two 3G standards, there is much less attention on TD-SCDMA, hence we focus on TD-SCDMA synchronization in this study.
So far, only few algorithms had been proposed for TD-SCDMA synchronization (Capaccioli and Rispo, 2003; Ventura and Hindelang, 2002). But these algorithms had huge computation loads due to the correlation operations, resulting in low applicability in real-world applications. Moreover, in order to degrade the complexity, some non-coherent initial algorithms were proposed before the correlation operations (Gao, 2005). However, these non-coherent methods can not accommodate with large SNR dynamic ranges, leading to limited complexity degradation. Accordingly, how to find a reliable and simple synchronizer in TD-SCDMA downlink is still unsolved.
By utilizing the non-coherent Power Ratio Detection (PRD) and Hypothesis Test (HT) instead of the conventional Power Detection (PD) and global peak searching, we design a simple and reliable algorithm for initial frame synchronization. Simulations show a good performance in a wide range of SNRs.
TD-SCDMA SIGNAL MODEL
The TD-SCDMA radio frame structure is shown as Fig. 1 (Chen et al., 2002), where one subframe (5 ms) is composed by seven traffic Time Slots (TS) and three special synchronization time slots: the downlink pilot timeslot (DwPTS), the uplink pilot timeslot (UpPTS) and guard period (GP).
In the seven TSs, TS0 and TS1 are always designated for downlink and uplink, while the other TSs can be allocated for either uplink or downlink according to the position of the switching point. In addition, DwPTS and UpPTS are used for initial cell synchronization.
|Fig. 1:||TD-SCDMA frame structure|
Next, suppose that the multipath fading channels are wide-sense stationary and mutually uncorrelated scattering (WSSUS) processes and the channel fading is approximately constant in a short duration. Then the receiving signals can be written as:
where, hl, x(n) and v(n) denote the channel coefficients, transmitted signals and additive complex white Gaussian noise (AWGN), respectively, φ denotes the time offset of frame start. In addition, the pulse shaping filter of transmitter and the match filter of receiver should be taken into account for a real-world application, i.e., hl has the influence of the two filters above, which is not considered in the conventional literature.
Generally, training sequence is used for frame start detection, which is SYNC_DL code in DwPTS in TD-SCDMA downlink. Ventura and Hindelang proposed to use maximum likelihood (ML) detection to match the SYNC_DL code:
where, the fading channel is assumed to be invariant within the duration of N chips and (.)* denotes the conjugate operation.
However, the computation and peak search of Λ(m) have very huge computation loads, i.e., 2621.44 millions complex multiplications per second (Ventura and Hindelang, 2002).
In order to reduce the complexity, some researchers calculate the correlation in frequency domain (Ventura and Hindelang, 2002). Unfortunately, the computational effort of this algorithm is 251 millions complex multiplications per second, which is still a huge burden for practical systems. Hence it is important to design a simple algorithm to reduce the computational effort.
Looking at Eq. 2, the huge computations are caused by the large searching range of m. Hence how to compress the peak searching range is an important way to reduce the complexity. Accordingly, some researchers indicated to use the non-coherent initial detection of GP before ML detection (Gao, 2005):
where, sign(.) represents the sign function, yr and yi denote the real part and the imaginary part of the receiving signals. In Eq. 3, T1 is used for binary decision thus has the value 0.5 (Kay, 1998; Proakis, 2001) and T2 is used for large number decision, which is 94 (Gao, 2005). However, the derivation of (3) ignores the influence of channel fading and transmitter pulse shaping, which will cause serious performance degradation for real-world synchronization systems.
According to the discussion above, we must set up a precise and simpler initial synchronization technique for real-world TD-SCDMA systems, which is very important to practical applications, such as the repeater, low cost terminal equipments and ultimately determines the total complexity reduction of the sequent ML detection.
NOVEL SYNCHRONIZATION ALGORITHM
Here we propose to find out the position of SYNC_DL code by detecting the inherent power transition of the special frame structure.
Let us look at the special frame structure of TD-SCDMA in Fig. 2 . Since the SYNC_DL code is QPSK-modulated and there is no signal being transmitted in GPs, resulting in high and low power in corresponding locations. Hence we can find the position of SYNC_DL by detecting power transition.
In Gao (2005), only the GPs are used to find the frame start, leading to poor performance in fading channel with large SNR variation. However, both SYNC_DL and GPs can be utilized to detect the power transition as demonstrated in the following.
First, we should define a detecting window as Fig. 3 , where W3 has only 80 chips to ensure pure noise samples in W3.
|Fig. 2:||Special frame structure of TD-SCDMA|
|Fig. 3:||Detecting windows|
The reason is that GP3 is followed by SYNC_UP and there are 16 chips transmitting forward in uplink. Subsequently, we define the power ratio as:
In Eq. 4, if m = θ, W2 collects the transmitted SYNC_DL as much as possible while W1 and W3 are almost pure noise samples, then η(m) will have a large and SNR-related value with high probability. Otherwise η(m) should have a smaller value. Hence, we can derive a novel initial synchronizer based on HT:
where, ηth denotes a determined threshold, which is determined as 1.75 by simulations in this study.
Note that conventional PD and HT methods can not select a determined threshold to cope with large SNR dynamic range, while our power ratio is related to the actual SNR so as to enhance the reliability in a large SNR dynamic range. Moreover, comparing with the conventional ML method, our HT method will explicitly lead to great complexity degradation in the followed correlation synchronizer.
SIMULATIONS AND ANALYSIS
This part of study presents a simulation system about TD-SCDMA downlink, which is designed according to practical applications and shown in Fig. 4. In Fig. 4, The TD-SCDMA downlink frames are pulse shaped then corrupted by fading and AWGN, subsequently the receiving signals are match filtered. Our novel algorithm acts as a bridge between the conventional correlation synchronizers and the match filter.
When performing simulations, we generate the multipath fading channel with ITU-R. M.1225 Power Delay Profile (PDP) (Xia and Wang, 2005). In this study, we consider root-raise-cosine (RRC) filters with roll off factor 0.22 in both transmitter and receiver, which is different from conventional studies. Note that four times over-sampling is used, resulting in the length extension of detecting window. Then, we denote subchip and chip as over-sampling signal and normal-sampling signal, respectively.
With the help of our PRD method, some correlation synchronizers can be followed, such as Eq. 2. However, it is beyond the scope of this study.
|Fig. 4:||Simulation model|
|Fig. 5:||A snapshot of (4): SNR = 3 dB, Frame time offset = 410x4 = 1640 subchips|
|Fig. 6:||Correct probability of (5) and (3): SNR = 6 dB|
In Fig. 5, we give a simulation snapshot of (4), where the SYNC_DL is started from the 5224th subchip (1640+TS0x4+GP2x4). From Fig. 5, we explicitly see that η(m) is rippled around 1 until near the 5224th subchip. Then if we choose the DwPTS start according to (5), we have precise time offset estimation.
In Fig. 6, we provide the results of the probability distribution of Eq. 5, where 10000 tests are carried out. From Fig. 6, we find that the proposed algorithm can achieve probability 0.8122 for zero synchronization error and 0.1591 for one chip absolute synchronization error.
|Fig. 7:||Correct probability of (5) in different SNRs|
Moreover, the probability is 0.0121 for more than two chips absolute synchronization error. These results are precise enough for many real-world applications. As a comparison, we provide the performance of (3) in 10000 test, where we only find 4.58% of the total tests have less than 6 chips absolute synchronization errors. The reason is that (3) does not take account for the influence of channel fading and large SNR dynamic range, however, these scenarios are popular in a real-world application.
In Fig. 7, we present the detecting probability in a desirable SNR range. The curves show that the correct detecting probability increases with the increase of SNR and our novel method owns a good performance in a wide range of SNRs, which is consistent with the analysis of section II. Although not shown in this figure, the corresponding result of Eq. 3 is very worse that the probability of less than 6 chips synchronization error is not exceeding 0.1.
As a conclusion, the proposed algorithm is very precise in SNR range 5~10 dB, which is the working SNR range for most practical communication systems. In detail, the probability approaches 0.9871 when at most two chips synchronization errors are considered, which is precise enough for most mobile applications and evidently will reduce the complexity of the subsequent correlation synchronizer.
We presented a precise and simpler algorithm for the initial downlink synchronization of TD-SCDMA system. Comparing with the traditional algorithms, the proposed algorithm has lower computation load and better performance in a wide range of SNRs. Furthermore, the correlation-based post-synchronizers (Ventura and Hindelang, 2002) can be operated after our algorithm to further improve the performance, which will be researched in the future.
The study is supported by the open research fund (Grant No.W200706) of National Mobile Communications Research Laboratory, Southeast University, China.
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