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Science Alert
 
   
 
    Publisher: Science Alert
   
  Singapore Journal of Scientific Research is a quarterly, peer-reviewed international research journal that addresses both applied and theoretical issues. The scope of the journal encompasses research articles, original research reports, reviews, short communications and scientific commentaries in the fields of applied and theoretical sciences, biology, chemistry, physics, zoology, medical studies, environmental sciences, mathematics, statistics, geology, engineering, agricultural engineering, computer science, social sciences, natural sciences, technological sciences, linguistics, medicine, industrial and all other applied and theoretical sciences.

Singapore Journal of Scientific Research now accepting new submissions. Submit your best paper via online submission system.
  Editor-in-Chief:  Anmol Mathur
 
 
Abhinav, B.S., M.J. Reddy, Y.S. Kumar and S. Sivanantham, 2015. ASIC design of reversible adder and multiplier. Int. J. Comput. Applic., 109: 6-10.
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Agarwal, A., P. Harsha, S. Vasishta and S. Sivanantham, 2014. Implementation of special function unit for vertex shader processor using hybrid number system. J. Comput. Networks Commun., Vol. 2014. 10.1155/2014/890354.
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Babu, A.R., R. Saikiran and S. Sivanantham, 2013. Design of floating point multiplier for signal processing applications. Int. J. Applied Eng. Res., 8: 715-722.
Kansagara, K., K.V. Shravya and S. Sivanantham, 2015. Dynalic Reconfigurable Architectures: A Boon for Desires of Real Time Systems. In: Information Systems Design and Intelligent Applications, Mandal, J.K., S.C. Satapathy, M.K. Sanyal, P.P. Sarkar and A. Mukhopadhyay (Eds.). Springer, India, ISBN: 978-81-322-2246-0, pp: 235-244.
Kumar, P.S., A. Verma, C. Patel and S. Sivanantham, 2014. Efficient floating point multiplier implementation via carry save multiplier. Middle-East J. Scient. Res., 22: 1652-1657.
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Singh, H., R. Heena and S. Sivanantham, 2014. ASIC implementation of two stage pipelined multiplier. Int. J. Eng. Res. Technol., 3: 1464-1466.
Sivanantham, S., 2013. Design of low power floating-point multiplier with reduced switching activity in deep submicron technology. Int. J. Applied Eng. Res., 8: 715-722.
Sivanantham, S., K.J. Naidu, S. Balamurugan and D.B. Phaneendra, 2013. Low power floating point computation sharing multiplier for signal processing applications. Int. J. Eng. Technol., 5: 979-985.
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Sivanantham, S., M. Padmavathy, G. Gopakumar, P.S. Mallick and J.R.P. Perinbam, 2014. Enhancement of test data compression with multistage encoding. Integration VLSI J., 47: 499-509.
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Sivanantham, S., M. Padmavathy, S. Divyanga and P.V.A. Lincy, 2013. System-on-a-chip test data compression and decompression with reconfigurable serial multiplier. Int. J. Eng. Technol., 5: 973-978.
Sivanantham, S., P.S. Mallick and J.R.P. Perinbam, 2014. Low-power selective pattern compression for scan-based test applications. Comput. Electr. Eng., 40: 1053-1063.
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Sivanantham, S., R. Adarsh, S. Bhargav and K.J. Naidu, 2014. Partial reconfigurable implementation of IEEE802.11g OFDM. Indian J. Sci. Technol., 7: 63-70.
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Suresh, B., P.T. Reddy, V.S.V. Srihari and S. Sivanantham, 2014. ASIC implementation of low power universal asynchronous receiver transmitter. World Applied Sci. J., 32: 472-477.
Valibaba, D.S. and S. Sivanantham, 2010. A survey on single and double edge-triggered flip-flops to design scan flip-flop cell. Programmable Device Circuits Syst., 2: 163-170.
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