Asian Science Citation Index is committed to provide an authoritative, trusted and significant information by the coverage of the most important and influential journals to meet the needs of the global scientific community.  
ASCI Database
308-Lasani Town,
Sargodha Road,
Faisalabad, Pakistan
Fax: +92-41-8815544
Contact Via Web
Suggest a Journal
Articles by Hu Jian-Ping
Total Records ( 3 ) for Hu Jian-Ping
  Yang Dan , Geng Ye-Liang and Hu Jian-Ping
  This study presents transmission gate flip-flop standard cells with channel length and dual-threshold techniques and their low-voltage operating. The proposed transmission gate flip-flops have the same structure with the basic master-slave transmission gate one using multiplexers, but the different place is the feedback path (non-critical path). In the non-critical path, the dual-channel length flip-flop uses high threshold devices while the dual-threshold flip-flop uses gate-length modulation device. Three flip-flop standard cells are investigated from 0.5 to 1.2 V in term of Energy Delay Product (EDP) with HSPICE at a SMIC 130 nm technology. The dual-threshold flip-flop standard cell achieves considerable leakage reductions and gate-length biasing flip-flop standard cell achieves the lowest total energy consumption in all the cells. The results demonstrate that scaling supply voltage using dual-threshold CMOS (low threshold and ultra high threshold) and gate-length biasing are advantageous, especially in low voltage regions (800-900 mv) which yield the best EDP.
  Xiang Xue-Cheng and Hu Jian-Ping
  In this study, standard cells based on single-rail MOS Current Mode Logic (SRMCML) for highspeed applications are developed and introduced into SMIC (Semiconductor Manufacturing International Corporation) 130 nm CMOS libraries which include basic logic gates such as inverter, NAND, NOR. The main design parameters including bias current, output voltage swing and device sizes of transistors in SRMCML cells are optimized to minimize Power Delay Product (PDP). The optimizations and designs for basic standard cells based on SRMCML are carried out. A full adder is verified with the proposed standard cells by using commercial EDA tools. Compared with the conventional static CMOS, the power delay product of the SRMCML AND and OR cells provide a reduction of 50.27 and 63.06% at 3 GHz, respectively. The results indicate the proposed SRMCML standard cells are a good choose in high-speed digital applications.
  Cheng Wei , Zhang Xia , Hu Jian-Ping and Han Cheng-Hao
  The leakage dissipation catches up with the dynamic power consumption gradually and it is becoming an important factor in low-power CMOS circuits. In this work, a p-type complementary pass-transistor adiabatic logic (P-CPAL) using DTCMOS and gate-length biasing techniques is proposed. In order to reduce sub-threshold leakage dissipations, DTCMOS and gate-length biasing techniques are used for the P-CPAL circuits. An ISCAS benchmark circuit using DTCMOS and gate-length biasing techniques is verified. All circuits are simulated with HSPICE using a NCSU 65nm PTM (Predictive Technology Model) process. Results show that both leakage and dynamic dissipations of the P-CPAL circuits with dual-threshold CMOS and gate-length biasing techniques are reduced greatly compared with the normal P-CPAL circuits.
Copyright   |   Desclaimer   |    Privacy Policy   |   Browsers   |   Accessibility