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Articles by Zhengliang Huang
Total Records ( 4 ) for Zhengliang Huang
  Qin Zheng , Yongheng Shang , Zhiyu Wang , Jiarui Liu , Min Zhou , Xiuqin Xu , Liping Wang , Hua Chen , Zhengliang Huang , Zheming Lu and Faxin Yu
  In this study, an automated testing system for a reflection-type Vector Modulators (VM) comprised of a Field Programmable Gate Array (FPGA) and a LabVIEW based testing software is presented. The testing system with a friendly Graphic User Interface (GUI) is able to evaluate all the functionality of the VMs and allows the user to test the FPGA module step-by-step or to automate the testing in a sequential way. In case of multiple VM testing, all the VMs can be tested in one time by automatically sending the control commands to manipulate the bias voltage of each VM. Only one FPGA based hardware is needed in the testing system for the bias voltage control. This present testing system is highly efficient for VM testing and can be easily generalized to the testing of other VMs.
  Liping Wang , Jiarui Liu , Huaqing Tong , Ming Hong , Yiqun Hu , Xiuqin Xu , Hua Chen , Zhiyu Wang , Yongheng Shang , Zhengliang Huang and Faxin Yu
  A novel highly integrated front-end T/R module with eight RF channels for the application of a K-band transceiver is presented. The proposed T/R module is based on the LTCC package combined with embedded microwave passive circuits and a variety of microwave transistor dies. Due to the applied multi-layer LTCC technology, the overall size and weight of the designed module is greatly reduced. Furthermore, such design improves the overall performance of the T/R module with a lower cost and high efficiency.
  Mengyao Su , Jiarui Liu , Hua Chen , Dongdong Liu , Min Zhou , Zhiyu Wang , Yongheng Shang , Zhengliang Huang and Faxin Yu
  This study presents a design of a highly reliable shift register based on TSMC 0.18 μm process which can efficiently fight against the Single Event Upset (SEU). A bilateral Power on Reset (POR) block, together with bit-line segregation and tri-mode redundancy technologies are applied in this design to comprehensively enhance the SEU hardening performance at both system level and circuit level. Assisted by the theory of transient circuit analysis, the shift register’s SEU hardening performance is achieved from the aspects of both schematic and layout. A current pulse which is used to emulate the SEU effect, is injected in the circuit for verification. The result of simulation shows great improvement of the SEU tolerance. With its high reliability and radiation tolerance, the present shift register can be applied to CMOS chip designs in the field of aerospace.
  Wei Chen , Xiuqin Xu , Hui Xu , Ming Hong , Zhiyu Wang , Yongheng Shang , Dongdong Liu , Min Zhou , Zhengliang Huang and Faxin Yu
  This study presents the temporal Coupled-Mode Theory (CMT) analysis of a K-band MMIC (Microwave Monolithic Integrated Circuit) bandpass filter with dual orthogonal resonant modes. Two test methods are applied and compared in the filter response measurement. The dimensions of the MMIC filter, whose chip size is 1.9×1.35 mm, are optimized based on the FEM (Finite Element Method) simulation assisted temporal coupled-mode theory. As a two-port reciprocal system, the transmission and reflection responses of the filter are deduced. GaAs MMIC IPD (Integrated Passive Device) technology is applied for chip fabrication. The test results using a probe station fit well with the simulation results. A testing fixture is introduced to model the practical application scenario, whose measurement results, after de-embedment, have shown consistency with the simulation and the probe station test results.
 
 
 
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