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Articles by Xiang Xue-Cheng
Total Records ( 1 ) for Xiang Xue-Cheng
  Xiang Xue-Cheng and Hu Jian-Ping
  In this study, standard cells based on single-rail MOS Current Mode Logic (SRMCML) for highspeed applications are developed and introduced into SMIC (Semiconductor Manufacturing International Corporation) 130 nm CMOS libraries which include basic logic gates such as inverter, NAND, NOR. The main design parameters including bias current, output voltage swing and device sizes of transistors in SRMCML cells are optimized to minimize Power Delay Product (PDP). The optimizations and designs for basic standard cells based on SRMCML are carried out. A full adder is verified with the proposed standard cells by using commercial EDA tools. Compared with the conventional static CMOS, the power delay product of the SRMCML AND and OR cells provide a reduction of 50.27 and 63.06% at 3 GHz, respectively. The results indicate the proposed SRMCML standard cells are a good choose in high-speed digital applications.
 
 
 
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