Articles by V. Elamaran (8)

Low Energy, Low Power Adder Logic Cells: A CMOS VLSI Implementation

S. Hari Hara Subramani, K.S.S.K. Rajesh and V. Elamaran

Asian Journal of Scientific Research 7 ( 2 ): 248 - 255 , 2014

CMOS VLSI Design of Low Power Comparator Logic Circuits

K.S.S.K. Rajesh, S. Hari Hara Subramani and V. Elamaran

Asian Journal of Scientific Research 7 ( 2 ): 238 - 247 , 2014

A Case Study of Impulse Noise Reduction Using Morphological Image Processing with Structuring Elements

V. Elamaran, Har Narayan Upadhyay, K. Narasimhan and J. Jezebel Priestley

Asian Journal of Scientific Research 8 ( 3 ): 291 - 303 , 2015

CMOS VLSI Design of Low Power SRAM Cell Architectures with New TMR: A Layout Approach

V. Elamaran and Har Narayan Upadhyay

Asian Journal of Scientific Research 8 ( 4 ): 466 - 477 , 2015

Low Power Digital Barrel Shifter Datapath Circuits Using Microwind Layout Editor with High Reliability

V. Elamaran and Har Narayan Upadhyay

Asian Journal of Scientific Research 8 ( 4 ): 478 - 489 , 2015

FPGA Implementation of Audio Enhancement using Xilinx System Generator

V. Elamaran, Kalagarla Abhiram and Narreddi Bhanu Prakash Reddy

Journal of Applied Sciences 14 ( 17 ): 1972 - 1977 , 2014

CMOS VLSI Implementation of Adders with Low Leakage Power

V. Elamaran, N. Raju, Anooj Krishnan and Kalagarla Abhiram

Journal of Applied Sciences 14 ( 14 ): 1550 - 1556 , 2014

A Novel Low Power Adder-Subtractor using Efficient XOR Gates

V. Elamaran, G. Rajkumar, S. Singh Rajpurohit and R. Anooj Krishnan

Journal of Applied Sciences 14 ( 14 ): 1623 - 1627 , 2014