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| Articles
by
Sundararaman Rajagopalan |
Total Records (
5 ) for
Sundararaman Rajagopalan |
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Sundararaman Rajagopalan
,
Har Narayan Upadhyay
,
Swetha Varadarajan
,
J.B.B. Rayappan
and
Rengarajan Amirtharajan
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The growing demand to protect the confidential messages and
documents paved way for the invent of information security techniques. Whatever,
be the strength of security algorithms and standards, an equal amount or greater
than that attempt is made to crack the information which employs an algorithm
to make it invisible to anonymous. New techniques and algorithms will help a
lot for strengthening the security of our information systems. Steganography
is basically a science turned art to hide the payload with the help of a carrier.
We propose a spatial domain image steganography technique which uses two aspects
for information hiding-one being the pixel nibble difference and the other in
the form of block rotation decided by a variable P’.
This technique adds a technique to the group of information hiding techniques
where block rotation can be decided by various parameters concerned with the
carrier which may be audio, video or text. |
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Sundararaman Rajagopalan
,
Yamini Ravishankar
,
Har Narayan Upadhyay
,
J.B.B. Rayappan
and
Rengarajan Amirtharajan
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Steganography, a protected envelope for information systems
is reaching new horizons at software as well as hardware level. Due to the number
of benefits that result in using reconfigurable hardware like FPGA for stego
system development, some attention is needed in performing the stego memory
testing. While Self test methodologies adopted for memories require attention
due to the extensive memory requirements, testing the secret carrier stego memory
modules occupies the center stage due to its higher importance of data protection.
Normally block RAMs inside FPGA can store the cover and stego images. With the
hardware pseudorandom pattern generators, the memory testing can be done effectively.
In this regard, the present work focuses on the implementation and analysis
of various combined multiple LFSR based pseudorandom sequence generation schemes
for Stego Memory self testing on Cyclone II EP2C20F484C7 FPGA. Analysis of the
different schemes for their suitability to stego memory arena is an important
objective of this work and also sequence distribution analysis has been carried
out to verify the distribution of pseudorandom sequences for N clock cycles.
The synthesis reports for all the four cases undertaken in this work have also
been reported. |
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Sundararaman Rajagopalan
,
Pakalapati J.S. Prabhakar
,
Mucherla Sudheer Kumar
,
N.V.M. Nikhil
,
Har Narayan Upadhyay
,
J.B.B. Rayappan
and
Rengarajan Amirtharajan
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Information hiding as a field is extremely fast developing and one of the very few fields that derive its power from its inherent need for sophistication and complexity in its algorithms. Out of the ever growing list of information hiding methods, steganography has emerged as the front runner because of clandestine nature. Image steganography is the heart of steganography because of wide availability of images in local media, variable capacity and its ability to cloak the very existence of secret data in it. There are innumerable software methods available for steganography but there is a dearth of hardware implementations to serve this purpose. In this study, we have devised a FPGA implementation that randomises the volume of data embedded in each pixel, according to the same MSBs. This implementation also contains a novel method to check the integrity of the embedded data by providing a mechanism by which we can weed out any modifications in the secret data, to an extent that it can even pinpoint the exact pixel in which the change has occurred. This algorithm has been implemented on EP2C35F672C6 FPGA. The synthesis report and Timing analysis have also been discussed in this study. |
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Sundararaman Rajagopalan
,
K. Pravallika
,
R. Radha
,
Har Narayan Upadhyay
,
J.B.B. Rayappan
and
Rengarajan Amirtharajan
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The inventions and innovations in the multimedia communication
have revolutionized the infotainment world. With the advancements in multimedia
, there is a growing demand to use the image, audio, video and text ingredients
for information protection. In the field of steganography, the cover to carry
over the secret information has been an image in many of the reported works
due to high payload carrying capacity. However audio steganography on hardware
platform provides the user an option to use multicarrier steganography on common
chip. Here we propose a method of steganography which has been implemented on
Cyclone II FPGA EP2C20F484C7 which houses an architecture with LSB substitution
of Huffman encoded secret message on select parts of digitized audio signal.
The experimental results show that a SNR of 127.7 dB has been obtained for 100
bits payload with embedding process done on every 2000th memory location of
16-bit digitized audio signal stored in External SRAM. |
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Sundararaman Rajagopalan
,
Rengarajan Amirtharajan
,
Har Narayan Upadhyay
and
John Bosco Balaguru Rayappan
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Little brooks make great rivers-says a proverb. Information science involves not only the efforts made for gathering, acquiring or collecting the data that corresponds to the information but also contains the ways to save it, protect it and preserve it. The meaning of the proverb however stresses upon how to protect and secure information, as a small leakage will pave way for entire loss of information which should be protected. True, there have been various methods, approaches and algorithms proposed in the past and will emerge in future too in the areas of secure information transmission. Cryptography and steganography have been primary sources for information security. The bird’s eye view on the literature pertaining to the above mentioned two giants of information security spots a number of algorithms developed on both software as well as hardware platforms. This study does the survey from the literature on different cryptographic and image steganographic methods implemented on a reconfigurable hardware like FPGAs in the past. The analysis of various methods proposed earlier is also an important objective of this study. |
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