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Articles by Pakalapati J.S. Prabhakar
Total Records ( 1 ) for Pakalapati J.S. Prabhakar
  Sundararaman Rajagopalan , Pakalapati J.S. Prabhakar , Mucherla Sudheer Kumar , N.V.M. Nikhil , Har Narayan Upadhyay , J.B.B. Rayappan and Rengarajan Amirtharajan
  Information hiding as a field is extremely fast developing and one of the very few fields that derive its power from its inherent need for sophistication and complexity in its algorithms. Out of the ever growing list of information hiding methods, steganography has emerged as the front runner because of clandestine nature. Image steganography is the heart of steganography because of wide availability of images in local media, variable capacity and its ability to cloak the very existence of secret data in it. There are innumerable software methods available for steganography but there is a dearth of hardware implementations to serve this purpose. In this study, we have devised a FPGA implementation that randomises the volume of data embedded in each pixel, according to the same MSBs. This implementation also contains a novel method to check the integrity of the embedded data by providing a mechanism by which we can weed out any modifications in the secret data, to an extent that it can even pinpoint the exact pixel in which the change has occurred. This algorithm has been implemented on EP2C35F672C6 FPGA. The synthesis report and Timing analysis have also been discussed in this study.
 
 
 
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