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Articles by M.R. Ahsan
Total Records ( 2 ) for M.R. Ahsan
  M. Niamul Bary , M. Habib Ullah , M.T. Islam and M.R. Ahsan
  This study is presented the feasibility of cross-referencing of exchange rates to estimate exchange rates on a short-term basis. The cross-referencing technique suggested herein was used to predict EURO currency based on the exchange rate relations modeled by using Artificial Neural Networks. Foreign exchange rates namely UK Pound (GBP), Switzerland Francs (CHF), Canadian Dollar (CAD) and Singaporean Dollar (SGD) have been selected to estimate the EURO currencies based on the data collected from the past 10 years from 1999 to 2008. The main objective this paper is to estimate EURO currency trend based on the cross-referenced relations with the other four currencies by using Artificial Neural Networks. Promising result is shown that the Artificial Neural Networks has been found to be appropriate for modeling and simulation in the data assessments. The paper gives detailed results regarding the use of Artificial Neural Networks for modeling EURO trends in terms of other currencies.
  M.R. Ahsan , M.I. Ibrahimy , O.O. Khalifa and M.H. Ullah
  Electromyography (EMG) signal based research is ongoing for the development of simple, robust, user friendly, efficient interfacing devices/systems. An EMG signal based reliable and efficient hand gesture identification system has been developed for human computer interaction which in turn will increase the quality of life of the disabled or aged people. The acquired and processed EMG signal requires classification before utilizing it in the development of interfacing which is the most difficult part of the development process. A back-propagation neural network with Levenberg-Marquardt training algorithm has been used for the classification of EMG signals. This study presents the neural network based classifier modeling using Hardware Description Language (HDL) for hardware realization. VHDL (Very High Speed Integrated Circuit Hardware Description Language) has been used to model the algorithm implemented into the target device FPGA (Field Programmable Gate Array). The designed model has been synthesized and fitted into Altera’s Stratix III, chipset EP3SE50F780I4L using the Quartus II version 9.1 Web Edition.
 
 
 
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